4

IX2R11

Figure 3. INPUT/OUPUT Timing Diagram

Symbol

Definition

Test Conditions

Min

Typ

Max

Units

V

INH

Logic “1” input voltage

V

7.0

V

V

INL

Logic “0” input voltage

V

6

V

V

I

0.28

V

V

V

I

.23

V

V

I

HL

HS to LS bias current.

V

.17

mA

I

QHS

Quiescent V

V

.77

mA

I

QLS

Quiescent V

V

.79

mA

I

QDD

Quiescent V

V

36

uA

I

Logic “1” input bias current

V

2uA

I

Logic “0” input voltage

V

1

uA

V

8.3

V

V

8.2

V

V

8.1

V

V

supply undervoltage negative going threshold.

8.0

V

I

HS or LS Output low short circuit current; V

+2

A

I

HS or LS Output low short circuit current; V

-2

A

Dynamic Electrical Characteristics

Symbol

Definition

Test Conditions

Min

Typ

Max Units

t

on

Turn-on propagation delay

V

120

ns

t

off

Turn-off propagation delay

V

87

ns

t

enb

Device Not enable delay

202

ns

t

r

Turn-on rise time

C

23

ns

t

f

Turn-off fall time

C

22

ns

t

dm

Delay matching, HS & LS turn-on/off

C

10

20

ns

Static Electrical Characteristics

Figure 4. ENABLE Waveform Definitions

Timing Waveform Definitions

HIN/LIN

ENB

LGO/HGO

ENB

LGO/HGO

10%

50%

tenb