ADCLK905/ADCLK907/ADCLK925

Data Sheet

Rev. B | Page 12 of 16

APPLICATIONS INFORMATION

POWER/GROUND LAYOUT AND BYPASSING

The ADCLK905/ADCLK907/ADCLK925 buffers are designed

for very high speed applications. Consequently, high speed design

techniques must be used to achieve the specified performance.

It is critically important to use low impedance supply planes for

as part of a multilayer board. Providing the lowest inductance

return path for switching currents ensures the best possible

performance in the target application.

It is also important to adequately bypass the input and output

supplies. A 1 µF electrolytic bypass capacitor should be placed

within several inches of each power supply pin to ground. In

addition, multiple high quality 0.001 µF bypass capacitors

supply pins and should be connected to the GND plane with

redundant vias. High frequency bypass capacitors should be

carefully selected for minimum inductance and ESR. Parasitic

layout inductance should be strictly avoided to maximize the

effectiveness of the bypass at high frequencies.

OUTPUT STAGES

The specified performance can be achieved only by using proper

transmission line terminations. The outputs of the ADCLK905/

ADCLK907/ADCLK925 buffers are designed to directly drive

800 mV into 50 Ω cable or microstrip/stripline transmission

output stage is shown in Figure 25. The outputs are designed for

best transmission line matching. If high speed signals must be

routed more than a centimeter, either the microstrip or the

stripline technique is required to ensure proper transition times

and to prevent excessive output ringing and pulse width-

dependent propagation delay dispersion.

Q

Q

Figure 25. Simplified Schematic Diagram of

the ADCLK905/ADCLK907/ADCLK925 PECL Output Stage

OPTIMIZING HIGH SPEED PERFORMANCE

As with any high speed circuit, proper design and layout

techniques are essential to obtaining the specified performance.

Stray capacitance, inductance, inductive power and ground

impedances, or other layout issues can severely limit performance

and cause oscillation. Discontinuities along input and output

transmission lines can also severely limit the specified jitter

performance by reducing the effective input slew rate.

In a 50 Ω environment, input and output matching have a

significant impact on performance. The buffer provides internal

50 Ω termination resistors for both D and D inputs. The return

side should normally be connected to the reference pin provided.

The termination potential should be carefully bypassed, using

ceramic capacitors to prevent undesired aberrations on the

input signal due to parasitic inductance in the termination

return path. If the inputs are directly coupled to a source, care

must be taken to ensure the pins are within the rated input

differential and common-mode ranges.

If the return is floated, the device exhibits 100 Ω cross termination,

but the source must then control the common-mode voltage

and supply the input bias currents.

There are ESD/clamp diodes between the input pins to prevent

the application of excessive offsets to the input transistors. ESD

diodes are not optimized for best ac performance. When a

clamp is desired, it is recommended that appropriate external

diodes be used.

BUFFER RANDOM JITTER

The ADCLK905/ADCLK907/ADCLK925 are specifically

designed to minimize added random jitter over a wide input

slew rate range. Provided sufficient voltage swing is present,

random jitter is affected most by the slew rate of the input signal.

Whenever possible, excessively large input signals should be

clamped with fast Schottky diodes because attenuators reduce the

slew rate. Input signal runs of more than a few centimeters

should be over low loss dielectrics or cables with good high

frequency characteristics.