AD9520-5 datasheet(8/74 Pages) AD

8 / 74 page

AD9520-5

Data Sheet

Rev. B | Page 8 of 74

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Source Current

Damage to the part can result if values are exceeded

Static

Dynamic

Sink Current

Damage to the part can result if values are exceeded

Static

Dynamic

TIMING CHARACTERISTICS

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL OUTPUT RISE/FALL TIMES

Termination = 50 Ω to VS_DRV − 2 V

Output Rise Time, tRP

130

170

20% to 80%, measured differentially (rise/fall times are

independent of VS and are valid for VS_DRV = 3.3 V and 2.5 V)

Output Fall Time, tFP

130

170

80% to 20%, measured differentially (rise/fall times are

independent of VS and are valid for VS_DRV = 3.3 V and 2.5 V)

PROPAGATION DELAY, tPECL, CLK-TO-LVPECL

OUTPUT

For All Divide Values

850

1050

1280

High frequency clock distribution configuration

800

970

1180

Clock distribution configuration

Variation with Temperature

1.0

ps/°C

OUTPUT SKEW, LVPECL OUTPUTS1

Termination = 50 Ω to VS_DRV − 2 V

LVPECL Outputs Sharing the Same Divider

VS_DRV = 3.3 V

VS_DRV = 2.5 V

LVPECL Outputs on Different Dividers

VS_DRV = 3.3 V

VS_DRV = 2.5 V

All LVPECL Outputs Across Multiple Parts

190

VS_DRV = 3.3 V and 2.5 V

CMOS OUTPUT RISE/FALL TIMES

Termination = open

Output Rise Time, tRC

750

960

20% to 80%; CLOAD = 10 pF; VS_DRV = 3.3 V

Output Fall Time, tFC

715

890

80% to 20%; CLOAD = 10 pF; VS_DRV = 3.3 V

Output Rise Time, tRC

965

1280

20% to 80%; CLOAD = 10 pF; VS_DRV = 2.5 V

Output Fall Time, tFC

890

1100

80% to 20%; CLOAD = 10 pF; VS_DRV = 2.5 V

PROPAGATION DELAY, tCMOS, CLK-TO-CMOS

OUTPUT

Clock distribution configuration

For All Divide Values

2.1

2.75

3.55

VS_DRV = 3.3 V

3.35

VS_DRV = 2.5 V

Variation with Temperature

ps/°C

VS_DRV = 3.3 V and 2.5 V

OUTPUT SKEW, CMOS OUTPUTS1

CMOS Outputs Sharing the Same Divider

VS_DRV = 3.3 V

105

VS_DRV = 2.5 V

All CMOS Outputs on Different Dividers

240

VS_DRV = 3.3 V

285

VS_DRV = 2.5 V

All CMOS Outputs Across Multiple Parts

600

VS_DRV = 3.3 V

620

VS_DRV = 2.5 V

OUTPUT SKEW, LVPECL-TO-CMOS OUTPUTS1

All settings identical; different logic type

Outputs Sharing the Same Divider

1.18

1.76

2.48

LVPECL to CMOS on same part

Outputs on Different Dividers

1.20

1.78

2.50

LVPECL to CMOS on same part

The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.

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