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CPC7512Z 数据表(PDF) 10 Page - IXYS Corporation |
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CPC7512Z 数据表(HTML) 10 Page - IXYS Corporation |
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10 / 18 page ![]() INTEGRATED CIRCUITS DIVISION CPC7512 10 www.ixysic.com R01 3. Functional Description 3.1 Introduction The CPC7512 Dual, 1Form-A, Shunt-Isolated High-Voltage, High-Frequency, Analog Switch has two symmetrical switch arrays with four operating states to facilitate switching of high-frequency, high-voltage signals using the AB and C switch states and the flexibility to provide a variety of alternative switching solutions for low-frequency high-voltage signal applications. Operational states and logical behavior of the device is shown in the “Truth Table” on page 8. Switch organization consists of two channels, each having three switches. Within each channel there is an independent LATCH input and a common Thermal Shutdown circuit that is shared by the two channels. Other than the shared TSD circuit, switch functionality under normal operating conditions within each channel is independent of the other channel. In designs where the switches will be required to carry high load currents or operate in higher temperature environments, the thermal specifications should be reviewed because the TSD circuit is shared by both channels. An excess thermal condition in one channel resulting in an active TSD event will cause an interruption in the other channel as well when the TSD protection circuit activates. Solid-state switch construction of the CPC7512 offers clean, bounce-free switching with simple TTL logic level input control to provide access to high voltage interfaces without the impulse noise generated by traditional electromechanical switching techniques. TTL logic level input control eliminates the additional driver circuitry required by traditional techniques. The low on-resistance (RON) symmetrical linear switches utilized in the AB switch state are configured as matched pairs, SW1A/SW1B and SW2A/SW2B, for improved performance when differential access is required. Their symmetrical construction provides an additional degree of design flexibility allowing either side of the switch to be connected to the high voltage network. Integrated into the CPC7512 switches are high frequency dynamic current limiting and thermal shutdown mechanisms to provide protection for the electronics being connected to a high voltage network during a fault condition. High frequency positive and negative transient currents such as lightning are reduced by the dynamic current limiting function while protection from prolonged low frequency power-cross and DC currents is provided by the thermal shutdown circuitry. To protect against a high voltage fault in excess of the CPC7512’s maximum voltage rating, use of an over-voltage protector is required. The protector must limit the voltage seen at the switch terminals to a level less than the switches’ breakdown voltage. To minimize the stress on the solid-state contacts, use of a foldback or crowbar type protector is highly recommended. With proper selection of the protector, telecom applications using the CPC7512 will meet all relevant ITU, LSSGR, TIA/EIA and IEC protection requirements. Operating from a single +5V supply the CPC7512 has extremely low power consumption. 3.2 Under-Voltage Switch Lock-Out Circuitry Smart logic in the CPC7512 provides for switch state control during both power up and power loss transients to prevent undesired connections to high voltage networks. This is done by setting the switches’ logic to the All-Off state. An internal detector evaluates the VDD supply against internally set thresholds to determine when to de-assert the under-voltage switch lock-out circuitry with a rising VDD, and when to assert the under-voltage switch lock-out circuitry with a falling VDD. Any time unsatisfactory low VDD conditions exist, the lock-out circuit overrides user switch control by blocking the external information applied to the input pins, output by the internal latch, and conditioning the internal switch commands to the All-Off state. Upon restoration of VDD, the switches will remain off until the LATCHx input is pulled low at which time proper conditioning of the SxIN0 and SxIN1 inputs must be made. The rising VDD lock-out release threshold ensures all internal logic is properly biased and functional before accepting external switch commands from the inputs. For a falling VDD event, the lock-out threshold is set to assure proper logic and switch behavior up to the moment the switches are forced off and external inputs are suppressed. |
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