CPC7512

R01

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3.3 Switch Logic

The CPC7512 under-voltage switch lock-out circuitry

switch behavior whenever the supply voltage is

inadequate.

The LATCH, depending on the logic level applied to it’s

pass the input data to the switch control logic. Once

the input data is passed to the switch control logic, the

value from the inputs will be locked by the LATCH

3.3.1 Data Latch

The CPC7512 has two integrated transparent data

latches, one for each channel. The latch-enable

operation is controlled by TTL input logic levels at the

the latch enable control pin, is at a logic 0 the data

latch is transparent and the input control signals flow

directly through the data latch to the state control

circuitry. A change in input will be reflected by a

change in the switch state.

Whenever the latch enable control pin is at logic 1, the

data latch is active and the control data is locked.

not result in a change to the control logic or affect the

existing switch states.

The switches will remain in the state they were in

will not respond to subsequent changes in input as

constrained by the latch function. Since internal

thermal shutdown control is not affected by the state of

the latch enable input, TSD will override state control.

3.3.2 TSD Pin Description

The TSD pin is a bidirectional I/O structure with an

output, this pin indicates the status of the thermal

shutdown circuitry of the CPC7512. During normal

under fault conditions that create excess thermal

loading, the entire device will enter thermal shutdown

and a logic low will be output at TSD.

As an input, the TSD pin can be used to place the

device into the All-Off state by simply pulling the input

low. This is a convenient way to temporarily place the

device’s switches into the off state without the need to

cycle the inputs and LATCH controls through an off

and then an on sequence. When TSD is released, the

device will revert back to it’s previous state.

When using TSD as an input, IXYS Integrated Circuits

Division recommends the use of an open-collector or

an open-drain type output to apply the logic LOW.

affect the CPC7512 thermal shutdown functionality.

The device ignores this input level and still enters the

thermal shutdown state at high temperature. In other

words, the thermal shutdown feature can not be

overridden by an external pull-up on the TSD control.

3.4 Power Supplies

Only a +5V logic supply and ground are required by

the CPC7512. Switch state control is powered

exclusively by the +5V supply. As a result, the

CPC7512 exhibits extremely low power consumption

during active and idle states.

3.5 Protection

The CPC7512 provides protection for both the low

voltage side circuitry it connects to high voltage

networks and itself. Two separate layers of protection

are interleaved within the device to protect against

high-energy high-frequency transients and

high-power, low-frequency fault conditions.

3.5.1 Dynamic High Frequency Current Limit

While in a closed switch state, high-frequency

high-energy current is restricted by the CPC7512. For

the telecom GR-1089-CORE specified +1000V

10x1000

s lightning pulse with a generator source

impedance of 10

 applied to the high voltage network

though a properly clamped external protector, the

current seen at the CPC7512 low voltage side

interface will be a pulse with a typical magnitude of 1A

and a duration less than 0.5

s.