CPC7524

R02

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11

When the latch enable control pin is at a logic 0 the

data latch is transparent and the input control signals

flow directly through the data latch to the state control

circuitry. A change in input will be reflected by a

change in the switch state.

Whenever the latch enable control pin is at logic 1, the

data latch is active and the control data is locked.

not result in a change to the control logic or affect the

existing switch states.

The switches will remain in the state they were in

will not respond to changes in input as long as the

affected by the latch function. Since internal thermal

shutdown control is not affected by the state of the

indicate the status of the thermal shutdown circuitry for

the associated channel. Typically, during normal

under fault conditions that create excess thermal

loading, the channel under duress will enter thermal

channel into the All-Off state by simply pulling the

input low. This is a convenient way to temporarily

place the channel’s switches into the off state without

the need to cycle the inputs and LATCH through an off

and then an on sequence.

For applications using logic devices powered from a

supply voltage that differs from the CPC7524, (lower

recommends the use of an open-collector or an

lower-voltage logic control, this avoids sinking the

operation when the All-Off state is not required. And

for higher logic-voltage control, this prevents

just ignores this input, and still enters the thermal

shutdown state at high temperature. In other words,

the thermal shutdown feature can not be overridden

3.4 Power Supplies

A +3.3V logic supply and ground are connected to the

CPC7524. Switch state control is powered exclusively

extremely low power consumption during active and

idle states.

3.5 Protection

The CPC7524 provides protection for both the low

voltage side circuitry it connects to high voltage

networks and itself. Three separate layers of

protection are interleaved within the device to protect

against high-energy high-frequency transients and

high-power, low-frequency fault conditions.

3.5.1 Dynamic High Frequency Current Limit

High voltage networks are ofttimes located in

environments susceptible to lightning events resulting

in high-frequency, high-energy transients being

coupled onto the high voltage network. Low voltage

circuits accessing high voltage networks through the

CPC7524 are protected from these events by the

dynamic high-frequency current-limit response

incorporated into each switch.

While in the ON state, the high frequency current is

restricted by the CPC7524. For a GR-1089-CORE

specified +1000V 10x1000

s lightning pulse with a

generator source impedance of 10

 applied to the

high voltage network though a properly clamped

external protector, the current seen at the CPC7524

low voltage side interface will be a pulse with a typical

magnitude of 1A and a duration less than 0.5

s.

3.5.2 Low Frequency Current Limit

During high-power, low-frequency faults, current

through a switch in the ON state will be constrained by

the low-frequency current-limit response of the switch.

As shown in “Figure 1: Switch Low Frequency

Response” on page 12 the low-frequency

current-limit response is dependent on the voltage

across the switch. For low levels of fault current the

graph shows that the voltage across the active switch

increases with increasing fault current. When the

magnitude of the fault current into the CPC7524