HTADC12 datasheet(7/12 Pages) HONEYWELL

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Functional Description

The A-to-D converter block consists of a 12-bit successive

approximation analog-to-digital converter using an internal 12-bit

capacitive charge re-distribution DAC. Conversions are initiated

by a high-to-low transition on the RNC input. The analog input

voltage range is from 0V to VREF_IN. While the conversion is in

progress, the Status output (STS) is high and the parallel data

outputs (D0 through D11) are in a high impedance state. When

the conversion is complete, the data is made available on the

parallel data output pins (D0 through D11). STS goes low

approximately 1.5 clock cycles after the data is placed on

the outputs, indicating that data is ready. A complete A/D

conversion cycle requires 38 clock cycles. The nominal internal

clock frequency is 4 MHz.

ADC Clocking: The internal A/D clock is nominally 4 MHz, and

is approximately temperature and supply independent. At the

nominal clock frequency the ADC throughput is approximately

100KSamples/sec.

Voltage Reference Options: The full-scale input range of the

ADC is 0V to VREFIN. The 12-bit ADC has an internal, buffered

reference source VREFOUT. VREFOUT is within 2.49V to 2.51V

over all conditions (-55°C to +225°C). The reference buffer is

designed to provide a low-impedance output capable of settling

within the sampling time of the ADC when operated with the

4MHz clock.

28 Pin Package: To use this reference connect VREFOUT

directly to VREFIN. Do not add decoupling capacitors at this

connection. The capacitance on VREFOUT should be minimized.

An external voltage reference may be used instead of the

internal reference source. In that case, the external source may

be connected directly to VREFIN and VREFOUT may be left

un-connected.

14 Pin Package: VREFOUT is connected to VREFIN inside

the package. No external reference can be used.

ADC Converter Control

Four signals are used to control the ADC.

• Conversion Control: CE, NCS, and RNC

• Output Buffer Control: CE, NCS, and RNC

• Output Format: A0

Conversion Control

It is recommended to use RNC as the signal to trigger the

conversion and read functions. CE and NCS should be used

as enables. Refer to timing diagrams.

However, the CE, NCS, and RNC have equivalent signal

functions. A conversion can be initiated by a transition on

the any of the control lines, as shown in the Truth Table.

Once a conversion is started, it can be terminated and restarted

by reasserting the appropriate control lines.

NCS

RNC

Operation

Outputs

None

High Impedance

None

High Impedance

Initiate conversion

High Impedance

Initiate conversion

High Impedance

Initiate conversion

High Impedance

Enable serial output

Enabled

Enable 12-bit parallel output

Enabled

(8 MSBs are read here when using 8-bit bus option)

Enable 4 LSBs + 4 trailing zeroes, all super-imposed on 8

Enabled

MSB outputs (8-bit bus option)

Truth Table

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