IMON

OUT

UVLO

+

Current

Sense

4.3 V

4.2 V

+

dVdT

2 µA

PORb

UVLOb

SWEN

24x

TPS16632

14

Ÿ

PLIM

65

Ÿ

X27.7 µ

x

ILIM

1.2 V

1.14 V

Ramp Control

Q

Q

SET

CLR

S

R

SHDNb

Current Limit Amp

Fast-Trip Comp

(Threshold= 40A)

PORb

Gate Control Logic

FLT

Charge

Pump

GND

TSD

PORb

UVLOb

SHDNb

Thermal

Shutdown

SHDN

Avdd

Fault Latch

Open/ Short

detect

Avdd

+

0.8V

SHDNb

TSD

OLR

SWEN

* Only for Latch Mode

P_IN

P_IN

MODE

OLR

162 msec

timer

Timeout

31

PŸ

5 V

Overload fault response

(Auto-Retry/Latch-off)

select detection

Avdd

Q

Q

SET

CLR

S

R

11.5 ms

10 µsec

PGOOD

65

Ÿ

Gate Enhanced

(HS_FET)

UVLOb

SHDNb

11.5 ms

10

IN

5 µA

Avdd

Gate Control Logic

10

TPS1663

SLVSET9A – SEPTEMBER 2018 – REVISED OCTOBER 2018

www.ti.com

Product Folder Links: TPS1663

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Copyright © 2018, Texas Instruments Incorporated

Functional Block Diagram (continued)

8.3 Feature Description

8.3.1 Undervoltage Lockout (UVLO)

fault, the internal FET quickly turns off and FLT is asserted. The UVLO comparator has a hysteresis of 60 mV.

To set the input UVLO threshold, connect a resistor divider network from IN supply to UVLO terminal to GND as

shown in the Typical Application circuit. If the Under-Voltage Lock-Out function is not needed, the UVLO terminal

must be connected to the IN terminal. UVLO terminal must not be left floating.