Si5321 datasheet(21/34 Pages) ETC

21 / 34 page

Si5321

Rev. 2.3

detected. When the input clock returns and is validated,

the device exits digital hold mode by re-locking to the

input clock without executing another self-calibration.

2.9. Bias Generation Circuitry

The Si5321 makes use of an external resistor to set

internal bias currents. The external resistor allows

precise generation of bias currents, which significantly

reduces power consumption and variation as compared

with traditional implementations that use an internal

resistor. The bias generation circuitry requires a 10 k

Ω

(1%) resistor connected between REXT and GND.

2.10. Differential Input Circuitry

The Si5321 provides a differential input for the clock

input, CLKIN. This input is internally-biased to a voltage

of VICM (see Table 2 on page 6) and may be driven by a

differential

single-ended

driver

circuit.

For

transmission line termination, the termination resistor is

connected externally as shown.

2.11. Differential Output Circuitry

The Si5321 utilizes a current mode logic (CML)

architecture to drive the differential clock output,

CLKOUT.

For single-ended output operation simply connect to

either CLKOUT+ or CLKOUT– and leave the unused

signal unconnected.

2.12. Power Supply Connections

The Si5321 incorporates an on-chip voltage regulator to

power the device from a 3.3 V supply. The voltage

regulator requires an external compensation circuit of

one resistor and one capacitor to ensure stability over

all operating conditions.

Internally, the Si5321 VDD33 pins are connected to the

on-chip voltage regulator input and to the device’s

LVTTL I/O circuitry. The VDD25 pins supply power to the

core DSPLL circuitry, and are also used for connection

of the external compensation circuit.

The regulator’s compensation circuit is a resistor and a

capacitor in series between the VDD25 node and ground.

Typically, the resistor is incorporated into the capacitor’s

equivalent series resistance (ESR). The target RC time

constant for this combination is 15 to 50

µs. The

capacitor used in the Si5321 evaluation board is a 33

µf

tantalum capacitor with an ESR of 0.8

Ω. This gives an

RC time constant of 26.4

µs. The Venkel part number

TA6R3TCR336KBR is an example of a capacitor that

meets these specifications. (See Figure 5.)

To get optimal performance from the Si5321 device, the

power supply noise spectrum must comply with the plot

in Figure 9. This plot shows the power supply noise

tolerance mask for the Si5321. The customer should

provide a 3.3 V supply that does not have noise density

in excess of the amount shown in the diagram.

However, the diagram cannot be used as spur criteria

for a power supply that contains single tone noise.

Figure 9. Power Supply Noise Tolerance Mask

Vn (µV/√Hz)

2100

10 kHz

500 kHz

100 Mhz

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