15

U4256BM-R

4562C–AUDR–08/04

7PDO

7.1

Saturation voltage

HIGH

3, 4

8.0

8.5

V

A

7.2

Saturation voltage

LOW

3, 4

0

0.4

V

A

8

SWO1, SWO2, SWO3, SWO4 (Open Drain)

8.1

Output leakage current

HIGH

Pin 7,8,9,10 over R

against 8.5 V

7, 8,

9, 10

I

SWOH

100

nA

A

8.2

Output voltage LOW

I = 1 mA

7, 8,

9, 10

V

SWOL

100

400

mV

A

9

DAC1, DAC2

9.1

Output current

3, 4

I

DAC1, 2

± 1mA

C

9.2

Output voltage

3, 4

V

DAC1, 2

0.3

V

V

A

9.3

Maximum offset range

(FM)

offset = 0, gain = 53

3, 4

0.45

0.56

0.65

V

A

9.4

Minimum offset range

(FM)

offset = 63, gain = 53

3, 4

-0.45

-0.57

-0.65

V

A

9.5

Maximum gain range

(FM)

gain = 255, offset = 31

3, 4

0.63

0.69

0.75

A

9.6

Minimum gain range

(FM)

gain = 0, offset = 31

3, 4

2.1

2.16

2.23

A

10

DAC3

10.1

Output current

5

I

DAC3

±1mA

C

10.2

Output voltage

Bit 68-66: 000

5

V

DAC3

0.4

0.55

0.7

V

A

10.3

Output voltage

Bit 68-66: 001

5

V

DAC3

1.1

1.25

1.4

V

A

10.4

Output voltage

Bit 68-66: 010

5

V

DAC3

1.8

1.90

2.1

V

A

10.5

Output voltage

Bit 68-66: 011

5

V

DAC3

2.4

2.60

2.8

V

A

10.6

Output voltage

Bit 68-66: 100

5

V

DAC3

3.2

3.30

3.5

V

A

10.7

Output voltage

Bit 68-66: 101

5

V

DAC3

3.8

4.10

4.3

V

A

10.8

Output voltage

Bit 68-66: 110

5

V

DAC3

4.5

4.80

5.0

V

A

10.9

Output voltage

Bit 68-66: 111

5

V

DAC3

5.2

5.45

5.7

V

A

11

3-wire Bus, ENABLE, DATA, CLOCK

11.1

Input voltage HIGH

LOW

16-18

V

BUSH

V

BUSL

2.7

-0.3

5.3

0.8

V

V

A

11.2

Clock frequency

17

1.0

MHz

A

11.3

Period of CLK HIGH

LOW

17

t

H

t

L

250

250

ns

ns

D

11.4

Rise time EN, DATA,

CLK

16-18

t

r

400

ns

D

11.5

Fall time EN, DATA,

CLK

16-18

t

f

100

ns

D

Electrical Characteristics (Continued)

No.

Parameters

Test Conditions

Pin

Symbol

Min.

Typ.

Max.

Unit

Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter