4

Copyright © 2007 IXYS CORPORATION All rights reserved

IXDR502 / IXDS502

Unless otherwise noted, 4.5V

≤ V

All voltage measurements with respect to GND. IXD_502 configured as described in Test Conditions.

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

High input voltage

4.5V

≤ V

3.5

V

Low input voltage

4.5V

≤ V

0.8

V

Input voltage range

-5

V

Input current

0V

≤ V

-20

20

µA

High output voltage

V

Low output voltage

0.05

V

Output resistance

@ Output high

6

Ω

Output resistance

@ Output Low

4

Ω

Continuous output

current

0.3

A

Rise time

14

ns

Fall time

12

ns

On-time propagation

delay

40

ns

Off-time propagation

delay

35

ns

Power supply voltage

4.5

15

22

V

Power supply current

1

0

3

10

10

mA

µA

µA

Notes:

1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanent

damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device

reliability.

2. The device is not intended to be operated outside of the Operating Ratings.

3. Electrical Characteristics provided are associated with the stated Test Conditions.

4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily

to highlight any specific performance limits within which the device is guaranteed to function.

1) The

θ

The

θ

J-A

of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated

by the resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with

vertical boards and the values would be lower with forced convection. For the 6-Lead DFN package, the

θ

package is soldered on a PCB. The

θ

provides a low thermal resistance to the die, it is easy to reduce the

θ

These can reduce the

θ

The

θ

management will vary significantly with size, construction, layout, materials, etc. This typical range tells the user what they are likely

to get if no thermal management is done.

2)

θ

The

θ

not published for the PDIP and SOIC packages. The

θ

junction to the die attach pad on the back of the DFN, -- and a guardband has been added to be safe.

3) The

θ

heatsink. The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily

available IMS in the U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was

assumed. The result was given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential

low thermal resistance for the DFN package.