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AD5721 数据表(PDF) 6 Page - Analog Devices

部件名 AD5721
功能描述  Multiple Range, 16-/12-Bit Bipolar/Unipolar, Voltage Output DACs
PDF  31 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD5721 数据表(HTML) 6 Page - Analog Devices

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AD5761/AD5721
Data Sheet
Rev. C | Page 6 of 31
TIMING CHARACTERISTICS
DVCC = 1.7 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
Limit at TMIN to TMAX
Unit
Description
t11
20
ns min
SCLK cycle time
t2
10
ns min
SCLK high time
t3
10
ns min
SCLK low time
t4
15
ns min
SYNC falling edge to SCLK falling edge setup time
t5
10
ns min
SCLK falling edge to SYNC rising edge time
t6
20
ns min
Minimum SYNC high time (write mode)
t7
5
ns min
Data setup time
t8
5
ns min
Data hold time
t9
10
ns min
LDAC falling edge to SYNC falling edge
t10
20
ns min
SYNC rising edge to LDAC falling edge
t11
20
ns min
LDAC pulse width low
t12
9
µs typ
DAC output settling time, 20 V step to 1 LSB at 16-bit resolution (see Table 3)
7.5
µs typ
DAC output settling time, 10 V step to 1 LSB at 16-bit resolution
t13
20
ns min
CLEAR pulse width low
t14
200
ns typ
CLEAR pulse activation time
t15
10
ns min
SYNC rising edge to SCLK falling edge
t16
40
ns max
SCLK rising edge to SDO valid (CL_SDO = 15 pF, where CL_SDO is the capacitive load on the SDO
output)
t17
50
ns min
Minimum SYNC high time (readback/daisy-chain mode)
1
Maximum SCLK frequency is 50 MHz for write mode and 33 MHz for readback mode.
Timing Diagrams
DB23
SCLK
SYNC
SDI
LDAC
CLEAR
VOUT
VOUT
VOUT
4
2
2
1
DB0
t12
t12
t10
t11
t14
t13
t9
t8
t7
t4
t6
t3
t2
t1
t5
Figure 2. Serial Interface Timing Diagram



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