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Data Sheet

AD5761/AD5721

Rev. C | Page 21 of 31

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER

The AD5761/AD5721 are single channel 16-bit/12-bit voltage

output DACs. The AD5761/AD5721 output ranges are software

selectable and can be configured as follows:

•

Unipolar output voltage: 0 V to 5 V, 0 V to 10 V, 0 V to 16 V,

0 V to 20 V

•

Bipolar output voltage: −2.5 V to +7.5 V, ±3 V, ±5 V, ±10 V

Data is written to the AD5761/AD5721 in a 24-bit word format

via a 4-wire digital interface that is serial peripheral interface

(SPI) compatible. The devices also offer an SDO pin to facilitate

daisy-chaining and readback.

TRANSFER FUNCTION

The input coding to the DAC can be straight binary or twos

complement (bipolar ranges case only). Therefore, the transfer

function is given by









−













REF

OUT

where:

VREF is 2.5 V.

M is the slope for a given output range (see Table 7).

D is the decimal equivalent of the code loaded to the DAC

0 to 4095 for the 12-bit device.

0 to 65,535 for the 16-bit device.

N is the number of bits. N is 12 for the AD5721 and 16 for the

AD5761.

C is the offset for a given output range (see Table 7).

Table 7. M and C Values for Various Output Ranges

Range

±10 V

±5 V

±3 V

2.4

1.2

−2.5 V to +7.5 V

0 V to 20 V

0 V to 16 V

6.4

0 V to 10 V

0 V to 5 V

DAC ARCHITECTURE

The DAC architecture consists of an R-2R DAC followed by an

output buffer amplifier. Figure 63 shows a block diagram of the

DAC architecture. Note that the reference input is buffered

prior to being applied to the DAC.

The output voltage range obtained from the configurable output

amplifier is selected by writing to the 3 LSBs, (RA[2:0]), in the

control register.

AGND

REFIN

CONFIGURABLE

OUTPUT

AMPLIFIER

OUTPUT

RANGE CONTROL

VREFIN

DAC REGISTER

VOUT

Figure 63. DAC Architecture

R-2R DAC

The architecture of the AD5761/AD5721 consists of two

matched DAC sections. A simplified circuit diagram is shown

in Figure 64. The six MSBs of the 16-bit data-word are decoded

to drive 63 switches, E0 to E62, whereas the remaining 10 bits of

the data-word drive the S0 to S9 switches of a 10-bit voltage

mode R-2R ladder network.

The code loaded into the DAC register determines which arms

of the ladder are switched between VREFIN and ground (AGND).

The output voltage is taken from the end of the ladder and

amplified afterwards to provide the selected output voltage.

10-BIT R-2R LADDER

SIX MSBs DECODED INTO

63 EQUAL SEGMENTS

E62

2R ...

...

E61

VOUT

VREFIN

AGND

Figure 64. DAC Ladder Structure

Reference Buffer

The AD5761/AD5721 operate with an external reference. The

reference input has an input range of 2 V to 3 V with 2.5 V for

specified performance. This input voltage is then buffered

before it is applied to the DAC core.

DAC Output Amplifier

The output amplifier is capable of generating both unipolar and

bipolar output voltages. It is capable of driving a load of 2 kΩ in

parallel with 1 nF to AGND. The source and sink capabilities of

the output amplifier are shown in Figure 37.

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