AD5669RBCBZ-1-R5 datasheet(24/30 Pages) AD

24 / 30 page

AD5629R/AD5669R

Data Sheet

Rev. F | Page 24 of 30

INPUT SHIFT REGISTER

The input shift register is 24 bits wide. Data is loaded into the

device as a 24-bit word under the control of a serial clock input,

SCL. The input register contents for this operation is shown in

Figure 53 and Figure 54. The eight MSBs make up the command

byte. DB23 to DB20 are the command bits, C3, C2, C1, and C0,

that control the mode of operation of the device (see Table 9 for

details). The last four bits of the first byte are the address bits,

A3, A2, A1, and A0, (see Table 9 for details). The rest of the bits

are the 16-/12-bit data-word.

The AD5669R data-word comprises the 16-bit input code (see

Figure 53) while the AD5629R data word is comprised of 12-

bits followed by four don’t cares (see Figure 54).

MULTIPLE BYTE OPERATION

Multiple byte operation is supported on the AD5629R/AD5669R.

Command 1001 is reserved for multiple byte operation (see

Table 8) A 2-byte operation is useful for applications that require

fast DAC updating and do not need to change the command

byte. The S bit (DB22) in the command register can be set to 1

for the 2-byte mode of operation. For standard 3-byte and 4-byte

operation, the S bit (DB22) in the command byte should be set to 0.

AD5669RBCBZ-1-R5 数据表(PDF) 24 Page - Analog Devices