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HT95L00P 数据表(PDF) 10 Page - Holtek Semiconductor Inc |
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HT95L00P 数据表(HTML) 10 Page - Holtek Semiconductor Inc |
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10 / 52 page  HT95LXXX Rev. 1.20 10 May 26, 2004 · Location 000CH (Bank0) This location is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, the Timer/Event Counter 1 interrupt is enabled and the stack is not full, the program begins execution at loca- tion 000CH. · Location 0014H (Bank0) This location is reserved for real time clock (RTC) in- terrupt service program. When RTC generator is en- abled and time-out occurs, the RTC interrupt is enabled and the stack is not full, the program begins execution at location 0014H. · Location 0018H (Bank0) This location is reserved for the HKS pin edge transi- tion or HDI pin falling edge transition or HFI pin rising edge transition. If this condition occurs, the dialer I/O interrupt is enabled and the stack is not full, the pro- gram begins execution at location 18H. Table Location Any location in the ROM space can be used as look-up tables. The instructions ²TABRDC [m]² (the current page, one page=256 words) and ²TABRDL [m]² (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). For the HT95L400/40P, the instruction ²TABRDC [m]² is used for any page of any bank. Only the destination of the lower-order byte in the table is well-defined, and the higher-order byte of the table word is transferred to TBLH. The table pointer (TBLP) or (TBHP, TBLP for the HT95L400/40P) is a read/write register (07H) or (1FH, 07H for the HT95L400/40P), which indicates the table location. Before accessing the table, the location must be placed in the (TBLP) or (TBHP, TBLP for the HT95L400/40P). The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read in- struction used in the ISR. Errors will then occur. Hence, simultaneously using the table read instruction in the main routine and the ISR should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt should be dis- abled prior to the table read instruction. It will not be en- abled until the TBLH has been backed-up. All table related instructions require two cycles to complete the operation. These areas may function as normal pro- gram memory depending on the requirements. HT95L400/40P Instruction(s) Table Location *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 TABRDC [m] #5 #4 #3 #2 #1 #0 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] 111111 @7 @6 @5 @4 @3 @2 @1 @0 HT95L300/30P, HT95L200/20P Instruction(s) Table Location *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 TABRDC [m] P12 P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] 11111 @7 @6 @5 @4 @3 @2 @1 @0 HT95L100/10P, HT95L000/00P Instruction(s) Table Location *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 TABRDC [m] P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] 1111 @7 @6 @5 @4 @3 @2 @1 @0 Note: *13~*0: Table location bits #7~#0: TBHP register bit7~bit0 @7~@0: TBLP register bit7~bit0 P12~P8: Current program counter bits |
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