8735AY-01

www.icst.com/products/hiperclocks.html

REV. F NOVEMBER 12, 2004

9

Integrated

Circuit

Systems, Inc.

ICS8735-01

The schematic of the ICS8735-01 layout example is shown in

Figure 5A. The ICS8735-01 recommended PCB board layout

for this example is shown in

Figure 5B. This layout example is

used as a general guideline. The layout in the actual system will

depend on the selected component types, the density of the

components, the density of the traces, and the stack up of the

P.C. board.

VCCO=3.3V

Bypass capacitor located near the power pins

R9

50

SEL0

VCC

RU6

1K

VCCO

CLK_SEL

C5

0.1uF

RD4

SP

3.3V

RD6

SP

(155.52 MHz)

Zo = 50 Ohm

R6

50

3.3V PECL Driver

LVPECL_input

+

-

R2

50

Zo = 50 Ohm

VCC=3.3V

R7

10

C7

0.1uF

SEL0

C2

0.1uF

C11

0.01u

Zo = 50 Ohm

(U1-9)

(U1-32)

VCC

RD2

1K

(U1-16)

C6

0.1uF

RD5

1K

R3

50

SEL1

RU5

SP

(77.76 MHz)

SEL[3:0] = 0101,

Divide by 2

RU4

1K

Output

Termination

Example

C16

10u

CLK_SEL

RD3

SP

RD7

1K

SP = Space (i.e. not intstalled)

VCC

U1

8735-01

1

2

3

4

5

6

7

8

17

18

19

20

21

22

23

24

SEL0

SEL1

CLK0

nCLK0

CLK1

nCLK1

CLK_SEL

MR

VCCO

nQ1

Q1

nQ2

Q2

nQ3

Q3

VCCO

VCCO

RU7

SP

(U1-24)

VCCA

RU3

1K

R10

50

(U1-17)

RU2

SP

PLL_SEL

R5

50

C1

0.1uF

(U1-25)

SEL2

SEL3

C4

0.1uF

VCC

R1

50

SEL2

R8

50

SEL1

R4

50

Zo = 50 Ohm

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS8735-01 provides

separate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required.

Figure 4 illustrates how

a 10

Ω resistor along with a 10µF and a .01µF bypass

capacitor should be connected to each V

10

Ω

V

CCA

10

µF

.01

µF

3.3V

.01

µF

V

CC