8735AY-01

www.icst.com/products/hiperclocks.html

REV. F NOVEMBER 12, 2004

1

Integrated

Circuit

Systems, Inc.

ICS8735-01

The ICS8735-01 is a highly versatile 1:5 Differ-

ential-to-3.3V LVPECL clock generator and a

member of the HiPerClockS™ family of High

Performance Clock Solutions from ICS. The

ICS8735-01 has a fully integrated PLL and can

be configured as zero delay buffer, multiplier or divider, and

has an output frequency range of 31.25MHz to 700MHz. The

reference divider, feedback divider and output divider are each

programmable, thereby allowing for the following output-to-

input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The

external feedback allows the device to achieve “zero delay”

between the input clock and the output clocks. The PLL_SEL

pin can be used to bypass the PLL for system test and debug

purposes. In bypass mode, the reference clock is routed

around the PLL and into the internal output dividers.

• 5 differential 3.3V LVPECL outputs

• Selectable differential clock inputs

• CLKx, nCLKx pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Output frequency range: 31.25MHz to 700MHz

• Input frequency range: 31.25MHz to 700MHz

• VCO range: 250MHz to 700MHz

• Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

• External feedback for “zero delay” clock regeneration

with configurable frequencies

• Cycle-to-cycle jitter: 25ps (maximum)

• Output skew: 25ps (maximum)

• Static phase offset: 50ps ± 100ps

• 3.3V supply voltage

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

HiPerClockS™

ICS

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

Top View

32-Lead VFQFN

5mm x 5mm x 0.95 package body

K Package

Top View

32 31 30 29 28 27 26 25

9

10 11 12 13 14 15 16

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

Q3

nQ3

Q2

nQ2

Q1

nQ1

SEL0

SEL1

CLK0

nCLK0

CLK1

nCLK1

CLK_SEL

MR

ICS8735-01

PLL_SEL

CLK0

nCLK0

CLK1

nCLK1

CLK_SEL

FB_IN

nFB_IN

SEL0

SEL1

SEL2

SEL3

MR

Q0

nQ0

Q1

nQ1

Q2

nQ2

Q3

nQ3

Q4

nQ4

0

1

PLL

8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8

0

1

÷1, ÷2, ÷4, ÷8,

÷16, ÷32, ÷64