ST 486 DX ASIC CORE

2/8

®

PRODUCT OVERVIEW

The ST 486 DX core is based on the design of the

SGS-THOMSON standard 486 DX4 product. The

core is capable of operating at the “external” bus

speed or at two or three times the bus speed up to

a maximum of 120MHz. Since the design is fully

static the core can operate at any frequency

between

D.C

and

120MHz.

The

core

is

manufactured on a high performance, low voltage,

five level metal, HCMOS 0.35 micron process to

achieve sub-nanosecond internal speeds while

offering very low power dissipation and high noise

immunity. The potential total gate count for

application specific devices exceeds 2 million

equivalent usable gates. The core operates over a

Vdd voltage range of 2.2 to 3.6 volts.

The core comes available with a full range of SSI,

MSI libraries as well as generators for SPRAM,

DPRAM, ROM.

Where process and design

philosophy permit it is possible to integrate

existing “standard DEVICES” within a 486 core

design. A full set of “chipset” function blocks are

available to build support subsystems on chip

blocks such as IDE controller, PCI bridge, DRAM

controller etc.

The I/O can be configured for circuits ranging from

low voltage CMOS and TTL to 200 MHz plus low

swing differential circuits.

CLOCK-TRIPLED CPU CORE

The ST486DX Core in DX4 mode provides up to

2.8 times the performance of a 486DX at the same

“external”

clock

frequency.

This

level

of

performance is achieved by tripling the frequency

of the input clock and using the resulting signal to

drive the CPU core.

To further enhance this

architecture, the ST486DX Core reduces the

performance penalty of slow external memory

accesses through use of an on-chip write-back

cache and eight write buffers.

The CPU core consists of a five-stage pipeline

optimized for minimal instruction cycle times and

includes all necessary hardware interlocks to

permit successive instruction execution overlap.

The execution stage of the pipeline executes

simple but frequently used instructions in a single

clock cycle and the hardware multiplier executes

16-bit integer multiplications in only three clocks.

ON-CHIP WRITE-BACK CACHE

The

ST486DX

Core on-chip cache

can

be

configured to run in traditional write-through mode

or in a higher performance write-back mode. The

write-back cache mode was specifically designed

to optimize performance of the CPU core by

eliminating

bus

bottlenecks

caused

by

unnecessary external write cycles.

This write-

back

architecture

is

especially

effective

in

improving

performance

of

the

clock-tripled

ST486DX4 Core.

Traditional

write-through

cache

architecture

require that all writes to the cache also update

external

memory

simultaneously.

These

unnecessary write cycles create bottlenecks which

result

in

CPU

stalls

and

adversely

impact

performance.

In

contrast,

a

write-back

architecture allows data to be written to the cache

without updating external memory. With a write-

back cache, external write cycles are only required

when a cache miss occurs, a modified line is

replaced in the cache, or when an external bus

master requires access to data.

The ST486DX Core cache is an 8-Kilobyte unified

instruction and data cache implemented using a

four-way set associative architecture and a least

recently used (LRU) replacement algorithm. The

cache is designed for optimum performance in

write-back mode, however, the cache can be

operated in write-through mode. The cache line

size is 16 bytes and new lines are only allocated

during memory read cycles.

Valid status is

maintained on a 16-byte cache line basis, but

modified or "dirty" status for write-back mode is

maintained on a 4-byte (double-word) basis.

Therefore, only the double-words that have been

modified are written back to external memory

when a line is replaced in the cache. The CPU

core can access the cache in a single internal

clock cycle for both reads and writes.

FPU OPERATIONS

Since the FPU is resident within the CPU, the

overhead

associated

with

external

maths

capriciousness cycles is eliminated. If the FPU is

not in use, the FPU is automatically powered

down.

This

feature

reduces overall

power

consumption.