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ST 486 DX ASIC CORE

®

SIMULATION ENVIRONMENT

The key area of the design flow is the simulation

environment that allows for multiple levels of

design abstraction to be simulated concurrently.

The

Cadence

Leapfrog/Verilog-XL

simulation

engine has been chosen for this “mix and match”

approach, allowing for gate level functional and

timing verification for individual modules to be

performed within a high level description of the

entire device.

CORE MODELS

The ST486DX core can be represented in the

simulation environment through different model

types such as a VHDL bus functional model or a

Model Source hardware model. The Model Source

option utilises ST486DX silicon interfaced to the

VHDL/Verilog software co-simulation environment

through a software shell.

SY ST EM

SY ST EM

SPEC IFIC ATION

BE H A VIO R AL

HDL

RTL HDL

SY NTHE SIS

PRE-L AYO UT

G ATE L EVEL

SIM U LATION

LAYOU T

PO ST-LAYO U T

G ATE L EVEL

SIM U LATION

M ANUFA C T.

AND TES T

L EV EL

1

CUSTO ME R

L EV EL

2

L EV EL

3

L EV EL

4

SG S-TH O M SO N

SG S-T H O M SO N

SG S-TH O M SO N

SG S-T H O M SO N

CUSTO M ER

CUSTO ME R

CUSTO M ER

Figure 3. Customer Interfaces

PACKAGE

NAME

84

100

120

128

144

160

168

176

180

196

208

224

225

256

257

304

313

400

480

GQ FP

PQFP

TQFP

BGA

Plastic

PGA

CP GA

POW

PQFP

with Slug

or

Spreader

: Packages in production

: Packages in development

NUMBER OF LEADS (Pins)

PACKAGE OPTIONS

Figure 2. Standard Package Options