CS5461 datasheet(21/46 Pages) CIRRUS

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CS5461

DS546PP2

the power/energy signals will be removed from the

CS5461’s power/energy results.

2. If the energy registration accuracy needs to be

within ±0.1% (with respect to reference calibration

levels on the voltage/current inputs) then either the

AC or the DC gain calibration is recommended for

the voltage/current channels.

3. Finally, run AC offset calibration on the voltage

and current channels.

4.5 Power Offset

The Power Offset Register can be used to offset

system power sources that may be resident in the

system, but do not originate from the power line

signal. These sources of extra energy in the system

contribute undesirable and false offsets to the pow-

er/energy measurement results. After determining

the amount of stray power, the Power Offset Reg-

ister can be set to nullify the effects of this unwant-

ed energy.

4.6 Phase Compensation

Bits 23 to 17 of the Configuration Register are used

to program the amount of phase delay added to the

voltage channel signal path. This phase delay is ap-

plied to the voltage channel signal in order to com-

pensate for phase delay that may be introduced by

the voltage and current sensor circuitry external to

the CS5461. Voltage and current transformers, as

well as other sensor equipment applied to the

front-end of the CS5461 inputs can often introduce

a phase delay in the system, which distorts the

phase relationship between the voltage and current

signals being measured. The phase compensation

bits PC[6:0] can be set to nullify this undesirable

phase distortion between the two channels.

The default value of the phase compensation bits is

0000000(b). This setting represents the shortest

time-delay (smallest phase delay) between the volt-

age and current channel signal paths. With the de-

fault setting, the phase delay on the voltage channel

is 0.995

µs (~0.0215 degrees assuming a 60 Hz

power signal). With MCLK = 4.096 MHz and

K = 1, the range of the internal phase compensation

ranges from -2.8 degrees to +2.8 degrees when the

input voltage/current signals are at 60 Hz. In this

condition, each step of the phase compensation reg-

ister (value of one LSB) is ~0.04 degrees. For val-

ues of MCLK other than 4.096 MHz, the range

(-2.8 to +2.8 degrees) and step size (0.04 degrees)

should be scaled by 4.096 MHz / (MCLK / K). For

power line frequencies other than 60 Hz, the values

of the range and step size of the PC[6:0] bits can be

determined by converting the above values to

time-domain (seconds), and then computing the

new range and step size (in degrees) with respect to

the new line frequency.

To calibrate the phase delay, use a purely resistive

load and adjust the phase compensation bits until

the Average Power Register value is maximized.

4.7 Time-Base Calibration

The Time-Base Calibration Register (notated as

“TBC” in Figure 2) is used to compensate for slight

errors in the XIN frequency. External oscillators

and crystals have certain tolerances. To improve

the accuracy of the clock for energy measurements,

the Time-Base Calibration Register can be manip-

ulated to compensate for the frequency error. Note

from Figure 2 that the TBC Register only affects

the value in the Average Power Register.

As an example, if the desired XIN frequency is

4.096 MHz, but during production-level testing the

average frequency of the crystal on a particular

board is measured to be 4.091 MHz. The ratio of

the desired frequency to the actual frequency is

4.096 MHz / 4.091 MHz = ~1.00122219506. The

Time-Base Calibration Register can be set to

1.00122213364 = 0x80280C(h), which is close to

the desired ratio.

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