ASIX ELECTRONICS CORPORATION

8

AX88178 L

USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller

3.0 Function Description

3.1 USB Core and Interface

The USB core and interface contains an USB 2.0 transceiver, serial interface engine (SIE), USB bus protocol

handshaking block, USB standard command, vendor command registers, logic for supporting bulk transfer, and interrupt

transfer, etc. The USB interface is used to communicate with USB host controller and is compliant with USB

specification V1.0, V1.1 and V2.0.

3.2 Gigabit MAC Core

The gigabit MAC core supports IEEE 802.3, 802.3u, and 802.3ab MAC sub-layer functions, such as basic MAC frame

receive and transmit, CRC checking and generation, filtering, forwarding, flow-control in full-duplex mode, and

collision-detection and handling in half-duplex mode, etc. It provides gigabit media-independent (GMII) and reduced

gigabit media-independent (RGMII) interface for interfacing with Gigabit Ethernet PHY.

3.3 Station Management (STA)

The station management interface provides a simple, two-wire, serial interface to connect to a managed PHY device for

the purposes of controlling the PHY and gathering status from the PHY. The station management interface allows

communicating with multiple PHY devices at the same time by identifying the managed PHY with 5-bit, unique Phy ID.

3.4 Memory Arbiter

The memory arbiter block is responsible for storing received MAC frames into on-chip SRAM (packet buffer) and then

forwarding to USB bus upon request from USB host via bulk in transfer. It also monitors packet buffer usage in

full-duplex mode for triggering PAUSE frame transmission out on TX direction. The memory arbiter block is also

responsible for storing MAC frames received from USB host via bulk out transfer and waiting to be transmitted out

towards Ethernet network.

3.5 USB to Ethernet Bridge

The USB to Ethernet bridge block is responsible for converting Ethernet MAC frame into USB packets or vice-versa.

This block supports proprietary burst transfer mechanism (submitted for US patent application) to offload software

burden and to offer very high packet transfer throughput over USB bus.

3.6 Serial EEPROM Loader

The serial EEPROM loader is responsible for reading configuration data automatically from external serial EEPROM

after power-on reset.

3.7 General Purpose I/O

There are 3 general purpose I/O pins provided by this ASIC.