19

ATSAM3303

6091A–DRMSD–07/04

External Memory

Pins used: WA21 - WA0: address out, WD15 - WD0: data bi-directional, WCS0, WCS1:

pre-decodes out, WOE: output enable, WWE: write

When using all address bits, the maximum address range is two pages (WCS0, WCS1)

of 4M words (total = 16 Mbytes).

Figure 12. ROM/Flash Read Cycle

Notes:

1. A built-in PLL multiplies the crystal clock frequency by 4 for internal use. p

PLL. p

2. Memory access time should be lower than t

WA0 - WA21

WD0 - WD15

WCS0

WOE

WCS1

Table 10. External Memory Parameters

Symbol

Parameter

Min

Typ

Max

Unit

t

RC

Read cycle time

5 * p

LCK

-6 * p

LCK

ns

t

CSOE

Chip select low/address valid to WOE low

2 * p

-

3 * p

ns

t

POE

Output enable pulse width

-

3 * p

LCK

-ns

t

ACE

Chip select/address access time

5 * p

-

-

ns

t

OE

Output enable access time

3 * p

-

-

ns

t

DF

Chip select or WOE high to input data Hi-Z

0

-

2 * p

ns