21

ATSAM3303

6091A–DRMSD–07/04

Reset and Power-

down

During power-up, the RESET input should be held low until the crystal oscillator and

PLL are stabilized, which takes max. 10ms.

After the low-to-high transition of RESET, the following occurs:

•

All P24s enter an idle state.

•

P16 program execution starts in built-in ROM.

The power-up sequence is as follows:

•

STIN is sensed. If HIGH, then the built-in debugger is started.

•

Addresses 0 & 1 from external ROM are checked. If “DR” is read, then control is

transferred to address 400H from external ROM.

•SMC is sensed. If LOW, then the built-in loader waits for SmartMedia presence

detect (SMPD). When detected, the firmware is downloaded from SmartMedia

reserved sector 1 and started.

•

An attempt is done to read the first two bytes of an external EEPROM or DataFlash.

If “DR” is read, then the built-in loader loads the firmware from the external

EEPROM/DataFlash and starts it.

•

Firmware download from a host processor is assumed.

1.

The byte 0ACh is written to the host, this rises IRQ. The host can recognize that

the chip is ready to accept program download. Higher speed transfer can be

reach by polling the parallel interface status (CS = 0, A0 = 1, RD = 0).

2.

The host sends the firmware size (in words) on two bytes (Low byte first).

3.

The host sends the ATSAM3303 firmware. The firmware should begin with string

“DR”.

4.

The byte 0ACh is written to the host, this rises IRQ. The host recognizes that the

chip has accepted the firmware.

5.

ATSAM3303 starts the firmware.

If PDWN is asserted low, then the crystal oscillator and PLL are stopped. If the power

switch is used, then the chip enters a deep power-down sleep mode, as power is

removed from the core. To exit power down, PDWN has to be asserted high, then

RESET applied.

Other power reduction features allowing warm restart are controlled by firmware:

•

P24s can be individually stopped.

•

The clock frequency can be internally divided by 256.