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W255
Document #: 38-07255 Rev. *C
Page 5 of 10
t4d
DDR Falling Edge Rate[3]
Measured between 20% to 80% of
output (refer to Figure 1)
0.5
1.50
V/ns
t5
Output to Output Skew for DDR[3] All outputs equally loaded
100
ps
t6
Output to Output Skew for
SDRAM[3]
All outputs equally loaded
150
ps
t7
SDRAM Buffer LH Prop. Delay[3]
Input edge greater than 1 V/ns
5
10
ns
t8
SDRAM Buffer HL Prop. Delay[3]
Input edge greater than 1 V/ns
5
10
ns
Switching Characteristics (continued)[4]
Parameter
Name
Test Conditions
Min.
Typ.
Max.
Unit
Switching Waveforms
Duty Cycle Timing
t1
t2
All Outputs Rise/Fall Time
OUTPUT
t3
3.3V
0V
0.4V
2.4V
2.4V
0.4V
t4
Output-Output Skew
t5
OUTPUT
OUTPUT
SDRAM Buffer HH and LL Propagation Delay
t6
INPUT
OUTPUT
t7
1.5V
1.5V
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