DSP56857 datasheet(39/662 Pages) FREESCALE

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5685x Family Architectural Overview

5685X Overview, Rev. 4

Freescale Semiconductor

1-7

1.3 5685x Family Architectural Overview

The 5685x family of devices consists of the 56800E core, program and data memory, including

peripherals useful for embedded control applications. Block diagrams for each chip describing

the differences in available peripheral sets and memory shown in the following figures:

Figure 1-1, Figure 1-2, Figure 1-3, Figure 1-4, and Figure 1-5.

Figure 1-1. 56853 Functional Block Diagram

JTAG/

Enhanced

OnCE

Program Controller

and

Hardware Looping Unit

Data ALU

16 x 16 + 36

→ 36-Bit MAC

Three 16-bit Input Registers

Four 36-bit Accumulators

Address

Generation Unit

Bit

Manipulation

Unit

16-Bit

56800E Core

XTAL

EXTAL

Interrupt

Controller

Quad

Timer

GPIOG

CLKO

External Address

Bus Switch

External Bus

Interface Unit

RESET

IRQA

IRQB

VDD

VSSIO

VDDA VSSA

External Data

Bus Switch

Bus Control

WR Enable

RD Enable

CS0-CS3[3:0] or

A0-20 [20:0]

MODEA-C or

D0-D15 [15:0]

Program Memory

12,288 x 16 SRAM

Boot ROM

1024 x 16 ROM

Data Memory

4,096 x 16 SRAM

PDB

XAB1

XAB2

XDB2

CDBR

SPI

GPIOF

2 SCI

GPIOE

IPBus Bridge (IPBB)

(GPIOH0-H2)

VDDIO

Decoding

Peripherals

System

Bus

Control

Memory

PAB

CDBW

CDBR

CDBW

VSS

GPIOA0-A3[3:0]

ESSI0

GPIOC

Host

Interface

GPIOB

RSTO

DMA

6 channel

POR

Integration

Module

System

COP/

Watch-

dog

Time

Day

Clock

Generator

OSC PLL

IPBus CLK

COP/TOD CLK

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