PIC18LF4520ESLASHSP datasheet(78/390 Pages) MICROCHIP

78 / 390 page

PIC18F2420/2520/4420/4520

DS39631A-page 76

Preliminary

 2004 Microchip Technology Inc.

6.2.2

TABLAT – TABLE LATCH REGISTER

The Table Latch (TABLAT) is an 8-bit register mapped

into the SFR space. The Table Latch register is used to

hold 8-bit data during data transfers between program

memory and data RAM.

6.2.3

TBLPTR – TABLE POINTER

The Table Pointer (TBLPTR) register addresses a byte

within the program memory. The TBLPTR is comprised

of three SFR registers: Table Pointer Upper Byte, Table

Pointer High Byte and Table Pointer Low Byte

(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-

ters join to form a 22-bit wide pointer. The low-order

21 bits allow the device to address up to 2 Mbytes of

program memory space. The 22nd bit allows access to

the device ID, the user ID and the configuration bits.

The Table Pointer register, TBLPTR, is used by the

TBLRD

and TBLWT instructions. These instructions can

update the TBLPTR in one of four ways based on the

table operation. These operations are shown in

Table 6-1. These operations on the TBLPTR only affect

the low-order 21 bits.

6.2.4

TABLE POINTER BOUNDARIES

TBLPTR is used in reads, writes and erases of the

Flash program memory.

When a TBLRD is executed, all 22 bits of the TBLPTR

determine which byte is read from program memory

into TABLAT.

When a TBLWT is executed, the six LSbs of the Table

Pointer register (TBLPTR<5:0>) determine which of the

64 program memory holding registers is written to.

When the timed write to program memory begins (via

the

bit),

the

MSbs

the

TBLPTR

(TBLPTR<21:6>) determine which program memory

block of 64 bytes is written to. For more detail, see

Section 6.5 “Writing to Flash Program Memory”.

When an erase of program memory is executed, the

16 MSbs of the Table Pointer register (TBLPTR<21:6>)

point to the 64-byte block that will be erased. The Least

Significant bits (TBLPTR<5:0>) are ignored.

Figure 6-3 describes the relevant boundaries of

TBLPTR based on Flash program memory operations.

TABLE 6-1:

TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

FIGURE 6-3:

TABLE POINTER BOUNDARIES BASED ON OPERATION

Example

Operation on Table Pointer

TBLRD*

TBLWT*

TBLPTR is not modified

TBLRD*+

TBLWT*+

TBLPTR is incremented after the read/write

TBLRD*-

TBLWT*-

TBLPTR is decremented after the read/write

TBLRD+*

TBLWT+*

TBLPTR is incremented before the read/write

TABLE ERASE/WRITE

TABLE WRITE

TABLE READ – TBLPTR<21:0>

TBLPTRL

TBLPTRH

TBLPTRU

TBLPTR<5:0>

TBLPTR<21:6>

PIC18LF4520E/SP 数据表(PDF) 78 Page - Microchip Technology

PIC18LF4520E/SP 数据表(HTML) 78 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载