9

logic high and then CE is brought

to logic low. Next, each

successive rising CLK edge will

shift in the data on the D

Finally, when 8 bits have been

loaded, the CE line is brought to

logic high. When CLK goes to

logic low, new data is copied into

the selected control word.

Loading data into the Control

Register takes place while the

previous control word configures

the display.

Control Word 0

Loading the Control Register with

D

Word 0 (see Table 2). Bits D

adjust the display brightness by

pulse width modulating the LED

on-time, while Bits D

the display brightness by

changing the peak pixel current.

Bit D

sleep mode.

Control Register

The Control Register allows

software modification of the IC’s

operation and consists of two

independent 7-bit control words.

Bit D

one of the two 7-bit control

words. Control Word 0 performs

pulse width modulation

brightness control, peak pixel

current brightness control, and

sleep mode. Control Word 1 sets

serial/simultaneous data out

mode, and external oscillator

prescaler. Each function is

independent of the others.

Control Register Data

Loading

Data is loaded into the Control

Register, MSB first, according to

the procedure shown in Table 1

and the Write Cycle Timing

Diagram. First, RS is brought to

columns by 8 rows. This array can

be conceptualized as four 5 x 8

dot matrix character locations,

but only 7 of the 8 rows have

LEDs (see Figures 1 & 2). The

bottom row (row 0) is not used.

Thus, latch location 0 is never

displayed. Column 0 controls the

left-most column. Data from Dot

Latch locations 0-7 determine

whether or not pixels in Column 0

are turned-on or turned-off.

Therefore, the lower left pixel is

turned-on when a logic high is

stored in Dot Latch location 1.

Characters are loaded in serially,

with the left-most character being

loaded first and the right-most

character being loaded last. By

loading one character at a time

and latching the data before

loading the next character, the

figures will appear to scroll from

right to left.

HCMS-29xx Write Cycle Diagram

NOTE:

1. DATA IS COPIED TO THE CONTROL REGISTER OR THE DOT LATCH AND LED OUTPUTS WHEN CE IS HIGH AND CLK IS LOW.

RSH

T

CES

T

CLKH

T

CLKL

T

CEH

T

DS

T

DH

T

CEDO

T

DOUT

T

DOUTP

T

PREVIOUS DATA

NEW DATA

12

11

4

3

5

1

6

2

7

10

8

9

NEW DATA LATCHED HERE

[1]

CE

RS

CLK

D

IN

LED OUTPUTS,

CONTROL

REGISTERS

(SIMULTANEOUS)

OUT

D

D

(SERIAL)

OUT