TLV9001UIDBVR datasheet(17/76 Pages) TI1

17 / 76 page

TLV9001, TLV9002, TLV9004

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SBOS833J – OCTOBER 2017 – REVISED JANUARY 2019

Product Folder Links: TLV9001 TLV9002 TLV9004

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Electrical Characteristics (continued)

For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25 °C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT =

VS / 2 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(1)

Specified by design and characterization; not production tested.

(2)

Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin

and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.

(3)

Full shutdown refers to the dual TLV9002S having both channels 1 and 2 disabled (SHDN1 = SHDN2 = V–) and the quad TLV9004S

having all channels 1 to 4 disabled (SHDN12 = SHDN34 = V–). For partial shutdown, only one SHDN pin is exercised; in this mode, the

internal biasing circuitry remains operational and the enable time is shorter.

POWER SUPPLY

Specified voltage range

1.8

(±0.9)

5.5

(±2.75)

Quiescent current per amplifier

TLV9002, TLV9002S TLV9004,

TLV9004S

IO = 0 mA, VS = 5.5 V

µA

TLV9001, TLV9001S

IO = 0 mA, VS = 5.5 V

IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C

SHUTDOWN(1)

IQSD

Quiescent current per amplifier

VS = 1.8 V to 5.5 V, all amplifiers disabled, SHDN = VS–

0.5

1.5

µA

ZSHDN

Output impedance during

shutdown

VS = 1.8 V to 5.5 V, amplifier disabled

10 || 2

GΩ || pF

High level voltage shutdown

threshold (amplifier enabled)

VS = 1.8 V to 5.5 V

(V–) +

0.9

(V–) +

1.1

Low level voltage shutdown

threshold (amplifier disabled)

VS = 1.8 V to 5.5 V

(V–) +

0.2 V

(V–) +

0.7 V

tON

Amplifier enable time (full

shutdown)(2)(3)

VS = 1.8 V to 5.5 V, full shutdown; G = 1, VOUT = 0.9 × VS / 2, RL

connected to V–

µs

Amplifier enable time (partial

shutdown)(2)(3)

VS = 1.8 V to 5.5 V, partial shutdown; G = 1, VOUT = 0.9 × VS / 2, RL

connected to V–

tOFF

Amplifier disable time(2)

VS = 1.8 V to 5.5 V, G = 1, VOUT = 0.1 × VS / 2, RL connected to V–

µs

SHDN pin input bias current

(per pin)

VS = 1.8 V to 5.5 V, V+ ≥ SHDN ≥ (V+) - 0.8 V

VS = 1.8 V to 5.5 V, V– ≤ SHDN ≤ V- + 0.8 V

150

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