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TLV9001UIDBVR 数据表(PDF) 25 Page - Texas Instruments

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部件名 TLV9001UIDBVR
功能描述  Low-Power, RRIO, 1-MHz Operational Amplifier for Cost-Sensitive Systems
PDF  76 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TLV9001UIDBVR 数据表(HTML) 25 Page - Texas Instruments

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TLV9001, TLV9002, TLV9004
www.ti.com
SBOS833J – OCTOBER 2017 – REVISED JANUARY 2019
Product Folder Links: TLV9001 TLV9002 TLV9004
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 Operating Voltage
The TLV900x family of op amps are for operation from 1.8 V to 5.5 V. In addition, many specifications such as
input offset voltage, quiescent current, offset current, and short circuit current apply from –40°C to 125°C.
Parameters that vary significantly with operating voltages or temperature are shown in the typical characteristics
section.
8.3.2 Rail-to-Rail Input
The input common-mode voltage range of the TLV900x family extends 100 mV beyond the supply rails for the
full supply voltage range of 1.8 V to 5.5 V. This performance is achieved with a complementary input stage: an
N-channel input differential pair in parallel with a P-channel differential pair, as shown in the Functional Block
Diagram. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 100 mV
above the positive supply, whereas the P-channel pair is active for inputs from 100 mV below the negative
supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in
which both pairs are on. This 100-mV transition region can vary up to 100 mV with process variation. Thus, the
transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to
(V+) – 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift,
and THD can degrade compared to device operation outside this region.
8.3.3 Rail-to-Rail Output
Designed as a low-power, low-voltage operational amplifier, the TLV900x family delivers a robust output drive
capability. A class-AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10 kΩ, the output swings to within 20 mV of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails.
8.3.4 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device
enters the saturation region, the charge carriers in the output devices require time to return to the linear state.
After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore,
the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew
time. The overload recovery time for the TLV900x family is approximately 850 ns.
8.3.5 Shutdown
The TLV9001S, TLV9002S and TLV9004S devices feature SHDN pins that disable the op amp, placing it into a
low-power standby mode. In this mode, the op amp typically consumes less than 1 µA. The SHDN pins are
active low, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic low. The
TLV9001S, TLV9002S and TLV9004S SHDN pins include internal pullup resistors that pull the voltage to V+
(enabling the amplifiers) when the SHDN pins are not connected to a signal.
The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown
feature lies around 620 mV (typical) and does not change with respect to the supply voltage. Hysteresis has
been included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown
behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage
between V– and V– + 0.2 V. A valid logic high is defined as a voltage between V– + 1.2 V and V+. The shutdown
pin must either be connected to a valid high or a low voltage or driven, and not left as an open circuit.



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