STC89LE52RC datasheet(112/165 Pages) STC

112 / 165 page

8-Bit Shift Register (Mode 0)

Mode 0, selected by writing 0s into bits SM1 and SM0 of SCON, puts the serial port into 8-bit shift register mode.

Serial data enters and exits through RXD, and TXD outputs the shift clock. Eight data bits are transmitted/

received with the least-significant (LSB) first. The baud rate is fixed at 1/12 the System clock cycle. The terms

"RxD" and "TxD" are misleading in this mode. The RxD line is used for both data input and output, and the TxD

line serves as the clock.

Transmission is initiated by any instruction that uses SBUF as a destination register. The “write to SBUF” signal

also loads a “1” into the 9

th position of the transmit shift register and tells the TX Control block to commence a

transmission. The internal timing is such that one full system clock cycle will elapse between "write to SBUF,"

and activation of SEND.

SEND transfers the output of the shift register to the alternate output function line of P3.0, and also transfers Shift

Clock to the alternate output function line of P3.1. At the falling edge of the Shift Clock, the contents of the shift

As data bits shift out to the right, “0” come in from the left. When the MSB of the data byte is at the output

position of the shift register, then the “1” that was initially loaded into the 9

th position is just to the left of the

MSB, and all positions to the left of that contains zeroes. This condition flags the TX Control block to do one last

shift and then deactivate SEND and set TI. Both of these actions occur after "write to SBUF".

Reception is initiated by the condition REN=1 and RI=0. After that, the RX Control unit writes the bits 11111110

to the receive shift register, and in the next clock phase activates RECEIVE. RECEIVE enables SHIFT CLOCK

to the alternate output function line of P3.1.At RECEIVE is active, the contents of the receive shift register are

shifted to the left one position. The value that comes in from the right is the value that was sampled at the P3.0

pin the rising edge of Shift clock.

As data bits come in from the right, “1”s shift out to the left. When the “0” that was initially loaded into the right-

most position arrives at the left-most position in the shift register, it flags the RX Control block to do one last shift

and load SBUF. Then RECEIVE is cleared and RI is set.

8.1 UART Mode of Operation

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