STC89LE52RC datasheet(116/165 Pages) STC

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9-Bit UART with Fixed Baud Rate (Mode 2)

When SM1=1 and SM0=0, the serial port operates in mode 2 as a 9-bit UART with a fixed baud rate. 11 bits

are transmitted through TXD or received through RXD. The frame data includes a start bit(0), 8 data bits, a

programmable 9th data bit and a stop bit(1). On transmit, the 9th data bit comes from TB8 in SCON. On receive,

the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 the System clock

cycle.

Baud rate in mode 2 =

SMOD/64) x SYSclk

Transmission is initiated by any instruction that uses SBUF as a destination register. The “write to SBUF”

signal also loads TB8 into the 9

th bit position of the transmit shift register and flags the TX Control unit that a

transmission is requested. Transmission actually happens at the next rollover of divided-by-16 counter. Thus the

bit times are synchronized to the divided-by-16 counter, not to the “write to SBUF” signal.

The transmission begins when /SEND is activated, which puts the start bit at TXD. One bit time later, DATA is

activated, which enables the output bit of the transmit shift register to TXD. The first shift pulse occurs one bit

time after that. The first shift clocks a “1”(the stop bit) into the 9

th bit position on the shift register. Thereafter,

only “0”s are clocked in. As data bits shift out to the right, “0”s are clocked in from the left. When TB8 of the data

byte is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the

left of that contains “0”s. This condition flags the TX Control unit to do one last shift, then deactivate /SEND and

set TI. This occurs at the 11

th divided-by-16 rollover after “write to SBUF”.

Reception is initiated by a 1-to-0 transition detected at RXD. For this purpose, RXD is sampled at a rate of

16 times whatever baud rate has been estabished. When a transition is detected, the divided-by-16 counter is

immediately reset, and 1FFH is written into the input shift register.

At the 7

th, 8th and 9th counter states of each bit time, the bit detector samples the value of RXD. The value accepted

is the value that was seen in at least 2 of the 3 samples. This is done to reject noise. In order to reject false bits, if

the value accepted during the first bit time is not a 0, the receive circuits are reset and the unit continues looking

for another 1-to-0 transition. If the start bit is valid, it is shifted into the input shift register, and reception of the

rest of the frame proceeds.

As data bits come in from the right, “1”s shift out to the left. When the start bit arrives at the leftmost position

in the shift register,(which is a 9-bit register in Mode-2 and 3), it flags the RX Control block to do one last shift,

load SBUF and RB8, and set RI. The signal to load SBUF and RB8 and to set RI is generated if, and only if, the

following conditions are met at the time the final shift pulse is generated.:

1) RI=0 and

2) Either SM2=0, or the received 9

th data bit = 1

If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met,

the stop bit goes into RB8, the first 8 data bits go into SBUF, and RI is activated. At this time, whether or not the

above conditions are met, the unit continues looking for a 1-to-0 transition at the RXD input.

Note that the value of received stop bit is irrelevant to SBUF, RB8 or RI.

116

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