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STC89LE52RC 数据表(PDF) 114 Page - STCmicro Technology Co,.Ltd

部件名 STC89LE52RC
功能描述  Enhanced 80C51 Central Processing Unit ,6T or 12T per machine cycle
PDF  165 Pages
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制造商  STC [STCmicro Technology Co,.Ltd]
网页  http://www.stcmicro.com/
标志 STC - STCmicro Technology Co,.Ltd

STC89LE52RC 数据表(HTML) 114 Page - STCmicro Technology Co,.Ltd

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8-Bit UART with Variable Baud Rate (Mode 1)
In mode 1 the STC89xx serial port operates as an 8-bit UART with variable baud rate. A UART, or "universal
asynchronous receiver/transmitter," is a device that receives and transmits serial data with each data character
preceded by a start bit(low) and followed by a stop bit(high). A parity bit is sometimes inserted between the last
data bit and the stop bit. The essential operation of a UART is parallel-to-serial conversion of output data and
serial-to-parallel conversion of input data.
In mode 1, 10 bits are transmitted through TXD or received through RXD. The frame data includes a start bit
(always 0), 8 data bits (LSB first) and a stop bit (always 1). For a receive operation, the stop bit goes into RB8 in
SFR – SCON. The baud rate is determined by the overflow rate of Timer 1 or Timer 2 .
Baud rate in mode 1 = (2
SMOD /32 ) x timer 1 overflow rate
or = (2
SMOD /16 ) x Timer 2 overflow rate
Transmission is initiated by any instruction that uses SBUF as a destination register. The “write to SBUF”
signal also loads a “1” into the 9
th bit position of the transmit shift register and flags the TX Control unit that a
transmission is requested. Transmission actually happens at the next rollover of divided-by-16 counter. Thus the
bit times are synchronized to the divided-by-16 counter, not to the “write to SBUF” signal.
The transmission begins with activation of SEND, which puts the start bit at TXD. One bit time later, DATA is
activated, which enables the output bit of the transmit shift register to TXD. The first shift pulse occurs one bit
time after that.
As data bits shift out to the right, zeroes are clocked in from the left. When the MSB of the data byte is at the
output position of the shift register, then the 1 that was initially loaded into the 9
th position is just to the left of the
MSB, and all positions to the left of that contain zeroes. This condition flags the TX Control unit to do one last
shift and then deactivate SEND and set TI. This occurs at the 10
th divide-by-16 rollover after “write to SBUF.”
Reception is initiated by a 1-to-0 transition detected at RXD. For this purpose, RXD is sampled at a rate of 16
times the established baud rate. When a transition is detected, the divided-by-16 counter is immediately reset,
and 1FFH is written into the input shift register. Resetting the divided-by-16 counter aligns its roll-overs with the
boundaries of the incoming bit times.
The 16 states of the counter divide each bit time into 16ths. At the 7
th, 8th and 9th counter states of each bit time,
the bit detector samples the value of RXD. The value accepted is the value that was seen in at least 2 of the 3
samples. This is done to reject noise. In order to reject false bits, if the value accepted during the first bit time is
not a 0, the receive circuits are reset and the unit continues looking for another 1-to-0 transition. This is to provide
rejection of false start bits. If the start bit is valid, it is shifted into the input shift register, and reception of the rest
of the frame proceeds.
As data bits come in from the right, “1”s shift out to the left. When the start bit arrives at the left most position
in the shift register,(which is a 9-bit register in Mode 1), it flags the RX Control block to do one last shift, load
SBUF and RB8, and set RI. The signal to load SBUF and RB8 and to set RI is generated if, and only if, the
following conditions are met at the time the final shift pulse is generated.
1) RI=0 and
2) Either SM2=0, or SM2=0 and the received stop bit = 1
If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the
stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time, whether or not the above
conditions are met, the unit continues looking for a 1-to-0 transition in RXD.
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