4.

Microprocessor Interfaces

FS501 can be directly connected to any microprocessor by pins of CS_, WR_, RD_, ALE, AD<3>, AD<2>,

AD<1>, AD<0>, and RQO. It can access the read/write of the control registers, handle interrupts, and access

the measure registers.

Control Registers

The Control registers are to control the status of internal components, such as the status of the multiplexer, TAP

of the digital filters, etc. All of them are 8-bit registers, and all of them are input/output ports that can be read

and written by the microprocessor. When reset is activated (RST_= 0), all the control registers are rest to 0. The

microprocessor can control the chip by setting the control registers, and read the values of the control registers

to check the status of the chip.

Table 2. The Address of Control Registers and Interrupt Registers.

AFT<7:0>

SCP<7:0>

SIN<7:0>

SRF<7:0>

RGD<7:0>

7

0

MSB

0

1

0

0

0

6

5

4

3

2

1

0

LSB

BPFTR

SINL<2:0>

SRFH<1:0>

SRFL<2:0>

SCMPH<3:0>

SINH<3:0>

0

Name

Address

00

01

02

03

04

05

ADG<7:0>

ENAD

06

SETADC

MISC1<7:0>

ENVDS

MISC2<7:0>

0

0

TPS1<1:0>

07

08

ENVCS

RCTEN

ACDIV

ACEN

FTR

0

CYS<1:0>

09

INTRG<7:0>

ADG<5:0>

ENXTL_

ENOSCO_

1

FSDIV

0

ENLBS

ENGNDR_

0

LBO

0

0

0

0

ENCP

0

0

HUNK

0

0

0

INSTA<1>

0

0

INSTA<0>

INTEN<1>

0

0

INTEN<0>

0

0

TPS2<1:0>

MODE<3:0>

Table 2 shows the control signals and the addresses of the control registers. There are 10

addresses, 00~09. The functions are briefly described in Table 3.

Table 3. Brief Description of the Function of FS501 Registers

Registers

Function

Refer to

MODE<3:0>

Selection of Thermistor or Voltage Measure

Section 7.1

RGD<5>

Selection of Thermistor Measure Switches

Table 8

SIN<7:0>

Input selection of the ADC and control signals of the pre filter.

Table 9 and Table 10

SRF<5:0>

Reference voltage selection of the ADC and control signals of the

pre filter

Table 11 and Table 12

SCP<7:4>

Path selection of CMPH

Table 13

AFT<6:4>

Enable controls of the op amps

Fig. 8

ADG<5:0>

Input gain setting of the ADC

Section 8.2

ADG<7:6>

Job setting of the ADC

Section 8.6

SETADC<7:6> ENVDS and ENVCS, programmable power supply setting.

Section 5.3

SETADC<5:4> CYS<1:0>, ADC offset voltage elimination mode setting

Section 8.4

SETADC<3:0> TPS2<1:0> and TPS1<1:0>, TPS2<1:0> and TPS1<1:0> are the

high speed TAP and high resolution TAP setting of the digital filter.

Section 8.3

MISC1<6,4:3> Setting of the clock generator

Table 7

MISC2<7>

ACBUF op amp switching mode

Section 7.3

MISC2<2>

If set, the CMPH signal will bypass ACBUF amplifier and directly

output through ACA

Fig. 8

MISC2<4>,

MISC2<0>

Setting of Power Low Detector

Section 5.4

MISC2<1>

ENGNDR_, the enable control of the output of internal power supply

ground of the analog parts.

Section 5.2

INTRG<4>

Interrupt status register

Section 4.2

INTRG<0>

Enable control of IRQO

Section 4.2