11..1

Analog Multiplex:

1. Low Pass Filter Input:

SINH[1:0]

00

01

10

11

Select

OPO

OPH

SGND

TEMPH

2. ADC Negative Input:

SINL[1:0]

00

01

10

11

Select

VRL

VRH

SGND

TEMPL

3. Low Pass Filter Output, ADC Positive Input:

SFTA[0]

0

1

Select

FTB

FTIN

4. External Filter Control: SFTA[1]=1, FTIN and FTB short; SFTA[1]=0, FTIN and FTB open.

5. Internal Reference Voltage Control: SVR0=1, (VRH,VRL) = 1V (at VDD=5V). SVR1=1,

SGND=1/2(VRH,VRL).

6. ADC Reference Voltage Negative Input:

SVRL

0

1

Select

VRL

AGND

7. ADC Reference Voltage Positive Input:

SVRH

0

1

Select

VRH

REFI

8. OPAMP Reference voltage Input:

SOPL[1:0]

00

01

10

11

Select

VRL

VRH

SGND

AGND

11..2

OPAMP

1.

OPEN is the OPAMP enable control signal.

2.

OPC [1:0] can set OPAMP input operation mode as follows, 00: +Offset, 01: -Offset, 10: 2KHz chopper

frequency, 11: 1KHz Chopper frequency.

11..3

The Operation of the Delta-Sigma () Modulator ADC

This high resolution ADC is designed by the technology of delta-sigma () modulator. The continuous

analog signals are sampled by a very high sampling rate that is much higher than the bandwidth of the input

signal. The delta-sigma modulator converts the input signal to a series of 1-bit codes. These 1-bit codes are

then fed to the digital filter to filter out the high frequency quantization noise to find high resolution digital

outputs. This kind of ADC quantizes one bit in the analog part, therefore, it has very good linearity. Because it is

in a fully differential configuration, the common mode rejection ratio (CMRR) is very high and can reduce the

common mode signals effectively.

ANALO

G

INTEGRATO

R

DIGITAL LOW PASS

DECIMATION

FILTER

COMPARATOR

ANALO

G

INPU

T

V

in

D

out

1, -1, -1, 1, 1, 1,....

V

DA

C

The Symbolic Diagram of the Delta-Sigma Analog-to-Digital Converter