MSM6896 datasheet(13/43 Pages) OKI

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¡ Semiconductor

MSM6895/6896

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Chip Enable signal input.

When CE is in digital "0" state, WR and RD are valid.

B1T, B2T, B1R, B2R

B channel interface inputs and outputs.

B1T and B2T are outputs, and B1R and B2R are inputs. Through channel control by the processor,

various data paths are set. The CODEC input and output signals are input and output via these

pins.

Initially the B1T and B2T outputs are fixed in a digital "1", and the B1R and B2R inputs are

neglected.

BR1, BR2, BT1, BT2

External digital inputs and outputs to the B-channel.

BR1 and BR2 are outputs, and BT1 and BT2 are inputs. Through channel control by processor,

the digital paths are set between these input and output pins and the B channel.

These signals are applied to another CODEC interface of three-party the speech path and to the

interface of 64 kbps at the rate adaptor circuit.

Initially the BR1 and BR2 outputs are fixed in a digital "1", and the BT1 and BT2 inputs are

neglected.

RESET

Reset signal input.

Digital "0" input to RESET makes all of internal control registers to be initialized. When powered

on, this RESET signal should be input for initializing the system.

TIME

Watchdog timer output.

When the processor does not reset the timer, the 500 ms period (Digital "0" : 4 ms) digital signal

is continuously output. When RESET is at digital "0", this timer is reset. And, in about 500 ms after

RESET goes to digital "1", the first timer output signal is issued and then the timer signal is output

at intervals of a 500 ms. If the CK8 signal is not input, the TIME signal is not output.

LML

Control signal output for external hold tone generator.

LML goes to digital "1" state when the hold tone transmit mode on transmit path or the hold

acknowledge tone mode on receive path is selected. During initialized state, LML is in digital "0"

state.

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