u

t

u

(IN)

(INRUSH)

(OUT)

dVdT

dV

V

I

C

I

C

dT

t

IMON

OUT

UVLO

+

Current

Sense

4.3 V

4.2 V

+

dVdT

2 µA

PORb

UVLOb

SWEN

25x

TPS16632

16

Ÿ

PLIM

70

Ÿ

X27.9 µ

x

ILIM

1.2 V

1.12 V

Ramp Control

Q

Q

SET

CLR

S

R

SHDNb

Current Limit Amp

Fast-Trip Comp

(Threshold= 45A)

PORb

Gate Control Logic

FLT

Charge

Pump

GND

TSD

PORb

UVLOb

SHDNb

Thermal

Shutdown

SHDN

4.17V

Fault Latch

Open/ Short

detect

2.7V

+

0.8V

SHDNb

TSD

OLR

SWEN

* Only for Latch Mode

P_IN

P_IN

MODE

OLR

162 msec

timer

Timeout

31

PŸ

5 V

Overload fault response

(Auto-Retry/Latch-off)

select detection

3V

Q

Q

SET

CLR

S

R

11.5 ms

10 µsec

PGOOD

65

Ÿ

Gate Enhanced

(HS_FET)

UVLOb

SHDNb

10 ms

1.2 Meg

IN

5 µA

4.17V

Power Limit Amp

14

TPS1663

SLVSET9C – SEPTEMBER 2018 – REVISED MARCH 2019

www.ti.com

Product Folder Links: TPS1663

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Copyright © 2018–2019, Texas Instruments Incorporated

Functional Block Diagram (continued)

9.3 Feature Description

9.3.1 Hot Plug-In and In-Rush Current Control

The devices are designed to control the inrush current upon insertion of a card into a live backplane or other

"hot" power source. This limits the voltage sag on the backplane’s supply voltage and prevents unintended resets

of the system power. The controlled start-up also helps to eliminate conductive and radiative interferences. An

external capacitor connected from the dVdT pin to GND defines the slew rate of the output voltage at power-on.

The fastest output slew rate of 24V/500 µs can be achieved by leaving dVdT pin floating. The inrush current can

be calculated using Equation 1.

(1)

where

(2)

Figure 15 illustrates in-rush current control performance of the device during Hot Plug-In.