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TPS16632RGET 数据表(PDF) 20 Page - Texas Instruments |
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TPS16632RGET 数据表(HTML) 20 Page - Texas Instruments |
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20 / 42 page ![]() VIN FLTb IIN 20 TPS1663 SLVSET9C – SEPTEMBER 2018 – REVISED MARCH 2019 www.ti.com Product Folder Links: TPS1663 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Feature Description (continued) (1) VIN = 24 V RILIM = 3 kΩ Figure 23. Start-Up With Short on Output 9.3.5 Output Power Limiting, PLIM (TPS16632 Only) In TPS16630, with a fixed overcurrent limit threshold the maximum output power limit increases linearly with supply input. Electrical Industrial process control equipment such as PLC CPU needs to comply with standards like IEC61010-1 and UL1310 for fire safety which require limited energy and power circuits. Limiting the output power becomes a challenge in such high power applications where the operating supply voltage range is wide. The TPS16632 integrate adjustable output power limiting functionality that simplifies the system design requiring compliance in accordance to this standard. Connect a resistor from PLIM to GND as shown in Figure 24 to set the output power limiting value. If output power limiting is not required then connect PLIM to GND directly. This disables the PLIM functionality. During an over power load event the TPS16632 limits the output power at the programmed value set by PLIM resistor. This indirectly results in the device operation in current limiting mode with steady state output voltage and current set by the load characteristics and PLIM = VOUT × IOUT. Figure 8 shows the output power limit and current limit characteristics of TPS16632 with 100 W power limit setting. The maximum duration for the device in power limiting mode is 162 msec (typical), tCL_PLIM(dly). After this time, the device operates either in auto-retry or latch off mode based on MODE pin configuration in Table 1. P(PLIM) = 1 x R(PLIM) (5) Here P(PLIM) is output power limit in watts, R(PLIM) is the power limit setting resistor in kΩ. During the output power limiting operation, FLT asserts after a delay of tCL_PLIM_FLT(dly). The FLT signal remains asserted until the over power load condition is removed and the device resumes normal operation. Figure 25 illustrate output power limiting performance of TPS16632 with 100 W setting for class-2 power supply designs . |
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