ADE7756ARSRL datasheet(12/32 Pages) AD

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REV. 0

ADE7756

–12–

ANALOG INPUTS

The ADE7756 has two fully differential voltage input channels.

The maximum differential input voltage for each input pair

(V1P/V1N and V2P/V2N) is

±1 V. In addition, the maximum

signal level on each analog input (V1P, V1N, V2P, and V2N) is

also

±1 V with respect to AGND.

Each analog input channel has a PGA (Programmable Gain

Amplifier) with possible gain selections of 1, 2, 4, 8, and 16.

The gain selections are made by writing to the Gain regis-

ter—see Figure 5. Bits 0 to 2 select the gain for the PGA in

Channel 1 and the gain selection for the PGA in Channel 2 is

made via bits 5 to 7. Figure 4 shows how a gain selection for

Channel 1 is made using the Gain register.

V1P

V1N

VIN

GAIN[7:0]

CH1OS[7:0]

GAIN (k) SELECTION

OFFSET ADJUST

( 32mV)

k VIN

Figure 4. PGA in Channel 1

In addition to the PGA, Channel 1 also has a full-scale input

range selection for the ADC. The ADC analog input range selec-

tion is also made using the Gain register—see Figure 5. As

mentioned previously, the maximum differential input voltage is

±1 V However, by using Bits 3 and 4 in the Gain register, the

maximum ADC input voltage can be set to 1 V, 0.5 V, or 0.25 V.

This is achieved by adjusting the ADC reference—see Reference

Circuit section. Table I summarizes the maximum differential

input signal level on Channel 1 for the various ADC range and

gain selections.

Table I. Maximum Input Signal Levels for Channel 1

Max Signal

ADC Input Range Selection

Channel 1

1 V

0.5 V

0.25 V

1 V

Gain = 1

0.5 V

Gain = 2

Gain = 1

0.25 V

Gain = 4

Gain = 2

Gain = 1

0.125 V

Gain = 8

Gain = 4

Gain = 2

0.0625 V

Gain = 16

Gain = 8

Gain = 4

0.0313 V

Gain = 16

Gain = 8

0.0156 V

Gain = 16

GAIN REGISTER*

CHANNEL 1 AND CHANNEL 2 PGA CONTROL

ADDR: 0AH

PGA 2 GAIN SELECT

000 = x1

001 = x2

010 = x4

011 = x8

100 = x16

*REGISTER CONTENTS SHOW POWER-ON DEFAULTS

PGA 1 GAIN SELECT

000 = x1

001 = x2

010 = x4

011 = x8

100 = x16

CHANNEL 1 FS

SELECT

00 = 1V

01 = 0.5V

10 = 0.25V

000

654

Figure 5. Analog Gain Register

It is also possible to adjust offset errors on Channel 1 and Channel

2 by writing to the Offset Correction Registers (CH1OS and

CH2OS respectively). These registers allow channel offsets in the

range

±20 mV to ±60 mV (depending on the gain setting) to be

removed. Note that it is not necessary to perform an offset correc-

tion in an Energy measurement application if HPF1 in Channel 1

is switched on. Figure 6 shows the effect of offsets on the real

power calculation. As can be seen from Figure 6, an offset on

Channel 1 and Channel 2 will contribute a dc component after

multiplication. Since this dc component is extracted by LPF2 to

generate the Active (Real) Power information, the offsets will

have contributed an error to the Active Power calculation. This

problem is easily avoided by enabling HPF1 in Channel 1. By

removing the offset from at least one channel, no error compo-

nent can be generated at dc by the multiplication. Error terms at

Cos(

ωt) are removed by LPF2 and by integration of the Active

Power signal in the Active Energy register (AENERGY[39:0]).

See Energy Calculation section.

V I

FREQUENCY – RADS/Sec

VOS IOS

VOS I

IOS V

DC COMPONENT (INCLUDING ERROR TERM)

IS EXTRACTED BY THE LPF FOR REAL

POWER CALCULATION

Figure 6. Effect of Channel Offsets on the Real Power

Calculation

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