STP16CL596

7/18

Table 9: Truth Table

Note 1: OUT0 to OUT15 = ON when Dn = H; OUT0 to OUT15 = OFF when Dn = L.

Figure 7: Timing Diagram

Note: The latches circuit holds data when the LE terminal is Low.

When LE terminal is at High level, latch circuit doesn’t hold the data it passes from the input to the output.

When OE terminal is at Low level, output terminals OUT0 to OUT15 respond to the data, either ON or OFF.

When OE terminal is at High level, it switches off all the data on the output terminal.

CLOCK

/LE

/OE

SERIAL-IN

OUT0 .................. OUT7 .................. OUT15

SDO

H

L

Dn

Dn ..... Dn - 7 ..... Dn -15

Dn - 15

L

L

Dn + 1

No Change

Dn - 14

H

L

Dn + 2

Dn - 2 ..... Dn - 5 ..... Dn -13

Dn - 13

X

L

Dn + 3

Dn - 2 ..... Dn - 5 ..... Dn -13

Dn - 13

XL

Dn + 3

OFF

Dn - 13