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MSM80C85AHJS 数据表(PDF) 10 Page - OKI electronic componets |
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MSM80C85AHJS 数据表(HTML) 10 Page - OKI electronic componets |
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10 / 29 page ![]() 10/29 ¡ Semiconductor MSM80C85AHRS/GS/JS 0 T2 ¥ ¥ TWAIT T3 ¥ ¥ T4 T1 ¥ T5 ¥ ¥ ¥ ¥ TS ¥ TS ¥ ¥ ¥ 1 1 1 ¥ ¥ ¥ 1 1 1 0 0 0 0 1 (1) 0 A8 – A15 AD0 – AD7 RD, WR INTA ALE Machine State Status & Buses Control ¥ T6 TRESET TS TS THALT THOLD TS TS TS TS TS 1 TS TS TS 1 1 1 1 0 0 0 ¥ ¥ ¥ 1 ¥ 1 ¥ ¥ ¥ 0 (2) ¥ 0 (2) S1, S0 IO/ M 1 ¥ 0 ¥ 0 (2) TS TS TS Table 3 MSM80C85AH Machine State Chart 0 = Logic "0" 1 = Logic "1" TS = High Impedance ¥ = Unspecified Notes: (1) ALE not generated during 2nd and 3rd machine cycles of DAD instruction. (2) IO/M = 1 during T4 - T6 of INA machine cycle. T1 PCH (High Order Address) (PC+1)H A8-15 T2 T3 T4 T1 T2 T3 T1 T2 M3 M2 M1 T3 T AD0-7 ALE CLK RD WR STATUS IO/M IO Port IO Port PCL S1S0(Fetch) 10 (Read) 01 Write 11 (Low Order Address) Data from Memory (Instruction) Data from Memory (I/O Port Address) Data to Memory or Peripheral (PC+1)L1 Figure 5 MSM80C85AH Basic System Timing |
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