MPC885CZP66 datasheet(72/92 Pages) FREESCALE

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MPC885/MPC880 Hardware Specifications, Rev. 3

Freescale Semiconductor

FEC Electrical Characteristics

15.1 MII and Reduced MII Receive Signal Timing

The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz + 1%. The reduced MII

(RMII) receiver functions correctly up to a RMII_REFCLK maximum frequency of 50 MHz + 1%. There is no

minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK

frequency – 1%.

Table 34 provides information on the MII and RMII receive signal timing.

Figure 72 shows MII receive signal timing.

Figure 72. MII Receive Signal Timing Diagram

15.2 MII and Reduced MII Transmit Signal Timing

The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz +1%. The RMII

transmitter functions correctly up to a RMII_REFCLK maximum frequency of 50 MHz +1%. There is no minimum

frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK frequency – 1%.

Table 34. MII Receive Signal Timing

Num

Characteristic

Min

Max

Unit

MII_RXD[3:0], MII_RX_DV, MII_RX_ERR to MII_RX_CLK setup

—

MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold

—

MII_RX_CLK pulse width high

35%

65%

MII_RX_CLK period

MII_RX_CLK pulse width low

35%

65%

MII_RX_CLK period

M1_RMII RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR to RMII_REFCLK

setup

4—

M2_RMII RMII_REFCLK to RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR

hold

2—

MII_RX_CLK (input)

MII_RXD[3:0] (inputs)

MII_RX_DV

MII_RX_ER

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