MPC885CZP133 datasheet(49/92 Pages) FREESCALE

49 / 92 page

MPC885/MPC880 Hardware Specifications, Rev. 3

Freescale Semiconductor

CPM Electrical Characteristics

Figure 46 shows the port C interrupt detection timing.

Figure 46. Port C Interrupt Detection Timing

12.3 IDMA Controller AC Electrical Specifications

Table 18 provides the IDMA controller timings as shown in Figure 47 to Figure 50.

Figure 47. IDMA External Requests Timing Diagram

Table 18. IDMA Controller Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

DREQ setup time to clock high

—

DREQ hold time from clock high 1

1 Applies to high-to-low mode (EDM=1)

TBD

—

SDACK assertion delay from clock high

—

SDACK negation delay from clock low

—

SDACK negation delay from TA low

—

SDACK negation delay from clock high

—

TA assertion to falling edge of the clock setup time (applies to external TA)7

—

Port C

(Input)

DREQ

(Input)

CLKO

(Output)

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