GPCE040A

© Generalplus Technology Inc.

Proprietary & Confidential

5

Oct 01, 2013

Version: 1.4

5. SIGNAL DESCRIPTIONS

Mnemonic

PIN No.

Type

Description

IOA [15:8]

IOA [7:0]

46 - 39

34 - 27

I/O

I/O

IOA [15:8]: bi-directional I/O ports.

IOA [7:0] can be software programmed to wakeup I/O pins.

IOA [6:0] can be optioned as ADC Line-in input.

IOB [15:11]

IOB 10

IOB 9

IOB 8

IOB 7

IOB 6

IOB 5

IOB 4

IOB 3

IOB 2

IOB 1

IOB 0

50 - 54

57

58

59

60

61

62

63

64

65

66

67

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

IOB [15:11]: bi-directional I/O ports.

IOB10 can also be selected as UART Transmitter (Tx).

IOB9 can also be Multi-duty cycle output of TimerB (BPWMO).

IOB8 can also be Multi-duty cycle output of TimerA (APWMO).

IOB7 can also be selected as UART receiver (Rx).

IOB6 is a bi-directional I/O ports.

IOB5 can also be selected as feedback signal with EXT2.

IOB4 can also be selected as feedback signal with EXT1.

IOB3 can also be selected as an external interrupt input pin (EXT2)(Negative-edge Triggered).

IOB2 can also be selected as an external interrupt input pin (EXT1)(Negative-edge Triggered).

IOB1 can also be selected as a serial interface data.(SDA).

IOB0 can also be selected as a serial interface clock (SCK).

DAC1

12

O Audio DAC1 output.

DAC2

13

O Audio DAC2 output.

X32I

2

I

Oscillator Crystal input.

X32O

1

O Oscillator Crystal output.

VCOIN

70

I

RC filter connection for PLL.

AGC

16

I

AGC control pin.

MICN

19

I

Microphone differential input (negative).

MICP

21

I

Microphone differential input (positive).

V2VREF

14

O 2.0V output voltage, 5.0mA of driving capability (can be used as external ADC Line_IN top

reference voltage).

MICOUT

18

O Microphone 1

OPI

17

I

Microphone 2

VEXTREF

23

I

ADC Line_IN top external reference voltage input pin.

VMIC

25

O Microphone power supply.

VADREF

22

O AD reference voltage (generated by internal AD converter).

VDD

5, 69

I

Positive supply for logic.

VSS

8, 10, 26, 71

I

Ground reference for logic and I/O pins.

VDDIO

37, 38, 56

I

Positive supply for I/O pins.

VSSIO

35, 36, 48

I

Ground reference for I/O pins.

AVDD

24

I

Positive supply for analog circuit including ADC, DAC and 2.0V regulator.

AVSS

15

I

Ground reference for analog circuit including ADC, DAC and 2.0V regulator.

RESET

68

I

An active low reset to the chip.

SLEEP

49

O Sleep mode (active high).

TEST

3

I

Connected to high for test mode, normally connected to GND (test mode disabled) or unconnected.

N/C

7, 9, 11, 20, 47, 55

I

Not used.

N/C

4

I

Do NOT bonding and connect this pin, if user binding this pin, IC will not work.

WDGOPT*

6

I

Bonded for watchdog disabled, unbonded for watchdog enabled.

Note*: WDGOPT is the watchdog option pin, selected by bonding option. Remain WDGOPT unbonded to enable the watchdog. In

contrast, bonding this pad will disable watchdog. The reason of placing WDTOPT adjacent to VDD is to facilitate connection

between VDD and WDGOPT when disabling watchdog is necessary. The layout of WDOGPT option pin is drawn in the right.

VDD

WDGOPT