GPCE040A datasheet(9/26 Pages) GENERALPLUS

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GPCE040A

Proprietary & Confidential

Oct 01, 2013

Version: 1.4

Special function in PortB

PortB

Special Function

Function Description

Note

IOB0

SCK

Serial interface clock

Refer to see SIO section

IOB1

SDA

Serial interface data

Refer to see SIO section

EXT1

External interrupt source 1(Negative-edge Triggered)

IOB2 set as input mode

IOB2

Feedback Output1

Works with IOB4 by adding a RC circuit between

them to get an OSC to EXT1 interrupt

IOB2 set as inverted output

EXT2

External interrupt source 2(Negative-edge Triggered)

IOB3 set as input mode

IOB3

Feedback Output2

Works with IOB5 by adding a RC circuit between

them to get an OSC to EXT2 interrupt

IOB3 set as inverted output

IOB4

Feedback Input1

IOB5

Feedback Input2

IOB7

UART Receiver

Refer to see UART section

IOB8

APWMO

TimerA PWM output

Refer to Timer/Counter section

IOB9

BPWMO

TimerB PWM output

Refer to Timer/Counter section

IOB10

UART Transmitter

Refer to UART section

Default state:

Pull Low

PWM:

Pulse Width Modulation

Refer to the above table, the configuration of IOB2, IOB3, IOB4,

and IOB5 involves feedback function in which an OSC frequency

can be obtained from EXT1 (EXT2) by simply adding a RC circuit

between IOB2 (IOB3) and IOB4 (IOB5).

6.8. Timer/Counter

The GPCE040A provides two 16-bit timers/counters, TimerA and

TimerB.

The TimerA is called a universal counter.

TimerB is a

general-purpose counter.

The clock source of TimerA comes

from the combination of clock source A and clock source B.

TimerB, the clock source is given from source C.

When timer

overflows, an INT signal is sent to CPU to generate a time-out

signal.

Clock of Source A

Clock of Source B

Clock of Source C

Fosc/2

2048Hz

Fosc/2

Fosc/256

1024Hz

Fosc/256

32768Hz

256Hz

32768Hz

8192Hz

TMB1

8192Hz

4096Hz

4Hz

4096Hz

2Hz

EXT1

EXT2

EXT1

Initially, write a value of N into a timer and select a desired clock

source, timer will start counting from N, N+1, N+2,... through FFFF.

An INT (TimerA/TimerB) signal is generated at the next clock after

reaching “FFFF” and the INT signal is transmitted to INT controller

for further processing.

At the same time, N will be reloaded into

timer and start all over again.

The clock source A is a high

frequency source and clock source B is a low frequency source.

The combination of clock source A and B provides a variety of

speeds to TimerA.

A “1” represents pass signal and not gating.

In contrast, “0” indicates deactivating timer.

The EXT1 and EXT2

are the external clock sources.

Moreover, counter can generate

time-out signal for input clock source to a four bits (16 levels)

PWM pulse width counter.

A variety of clock duration can be

generated

and

exported

from

IOB8

(APWMO)

and

IOB9

(BPWMO).

The following example is a 3/16-duration cycle.

The APWMO

waveform

made

selecting

pulse

width

through

Port_TimerA_Ctrl (W) [9:6].

As a result, each 16 cycles will

generate a pulse width defined in control port.

These PWM

signals can be applied for controlling the speed of motor or other

devices.

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