CMOS Clock Generator – 74ACT3301

Rev 1.1

06/05/19

Configuration Options

Each configuration comprises one output with the choice of selected

frequency divide, output enable, crystal drive and output rise/fall time.

OUTPUT

RISE / FALL

TIME (ns)

DIVIDE

ENABLE

DRIVE

Crystal drive options:

L = Low drive

M = Medium drive

H = High drive.

1,2,4

OEH

L, M, H

2, 4

1,2,4

OEH

H

2, 4

8, 16, 32

OEH

H

4

8, 16, 32

OEH

L, M, H

4

1,2,4

OEL

H

1, 2

4

OEH

H

4

32

OEH

H

4

1,2,4

OEH

H

1, 2

1,2,4

OEL

L, M, H

2, 4

Pad Descriptions

INPUTS

OSC_IN (Pad 17) - Input to Oscillator Inverter. The output of the crystal would be connected here.

CONTROL INPUTS

DIVA (Pad 12) - Input used to select Binary Divide-By Option. This pin has CMOS compatible input levels.

DIVB (Pad 14) - 3 Level input used to select Binary Divide-By value.

DIVBB (Pad 16) - This pin is the same signal DIVB and provided as an alternative connection for hybrid assemblies.

OSC_DR (Pad 13) - 3 Level input pin that selects Oscillator Drive Level.

OEH (Pad 6) - Active High Three-state enable pin. This pin pulls to a high value when left floating and three-states the output when

forced low. This pin has TTL compatible input levels.

OEL (Pad 5) - Active Low Three-state enable pin. This pin pulls to a low value when left floating and three-states

the output when forced high. This pin has TTL compatible input levels.

TRF (Pad 11) - Rise and Fall time override pin

OUTPUTS

OUT (Pad 9) - This pin is the main clock output on the device.

OSC_OUT (Pad 1) - Resistive buffered output of the Oscillator inverter

OTHER PADS

OSC_LO_1 (Pad 7) - The Oscillator Low pin is the ground for the Oscillator.

OSC_LO_2 (Pad 15) - This pin is the same signal as OSCLO_1 and provided as an alternative connection for hybrid assemblies.

VCC (Pad 10) - The power pin for the chip.

GND (Pad 8) - The ground pin for all sections of the circuitry except the oscillator and oscillator related circuitry.

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