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HN58V65API-10 数据表(PDF) 19 Page - Renesas Technology Corp |
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HN58V65API-10 数据表(HTML) 19 Page - Renesas Technology Corp |
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19 / 28 page ![]() HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series Rev.3.00, Feb.02.2004, page 19 of 26 Functional Description Automatic Page Write Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write cycle. Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each additional byte load cycle must be started within 30 µs from the preceding falling edge of WE or CE. When CE or WE is kept high for 100 µs after data input, the EEPROM enters write mode automatically and the input data are written into the EEPROM. Data Polling Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read mode during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the EEPROM is performing a write operation. RDY/ Busy Signal RDY/ Busy signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high impedance except in write cycle and is lowered to VOL after the first write signal. At the end of a write cycle, the RDY/ Busy signal changes state to high impedance. RES Signal (only the HN58V66A series) When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping RES low when V CC is switched. RES should be high during read and programming because it doesn’t provide a latch function. V Program inhibit CC RES Program inhibit Read inhibit Read inhibit |
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