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PSD813F1 数据表(PDF) 1 Page - STMicroelectronics |
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PSD813F1 数据表(HTML) 1 Page - STMicroelectronics |
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1 / 110 page  1/110 August 2004 PSD813F1 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V FEATURES SUMMARY s DUAL BANK FLASH MEMORIES – 1 Mbit of Primary Flash Memory (8 Uniform Sectors) – 256 Kbit Secondary EEPROM (4 Uniform Sectors) – Concurrent operation: read from one memory while erasing and writing the other s 16 Kbit SRAM (BATTERY-BACKED) s PLD WITH MACROCELLS – Over 3,000 Gates Of PLD: DPLD and CPLD – DPLD - User-defined Internal chip-select decoding – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs) s 27 RECONFIGURABLE I/Os – 27 individually configurable I/O port pins that can be used for the following functions: MCU I/Os; PLD I/Os; Latched MCU address output; and Special function I/Os. Note: 16 of the I/O ports may be configured as open-drain outputs. s ENHANCED JTAG SERIAL PORT – Built-in JTAG-compliant serial port allows full-chip In-System Programmability (ISP) – Efficient manufacturing allows for easy product testing and programming s PAGE REGISTER – Internal page register that can be used to expand the microcontroller address space by a factor of 256. s PROGRAMMABLE POWER MANAGEMENT Figure 1. Packages s HIGH ENDURANCE: – 100,000 Erase/WRITE Cycles of Flash Memory – 10,000 Erase/WRITE Cycles of EEPROM – 1,000 Erase/WRITE Cycles of PLD – Data Retention: 15-year minimum at 90°C (for Main Flash, Boot, PLD and Configuration bits). s SINGLE SUPPLY VOLTAGE: – 5V±10% for 5V s STANDBY CURRENT AS LOW AS 50µA PQFP52 (M) PLCC52 (J) TQFQ64 (U) |
类似零件编号 - PSD813F1 |
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类似说明 - PSD813F1 |
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