NM1482KSLAXCL datasheet(89/121 Pages) NANYA

89 / 121 page

Version 1.6

Nanya Technology Corp.

05/2018

4Gb SLC NAND + 2Gb LPDDR2

NM148(F)2KSLAXCL/NM1482NSLAXCL

NTC Proprietary

Level: Property

Input / Output Capacitance

TOPER; VDDQ = 1.14-1.3V; VDDCA = 1.14-1.3V; VDD1 = 1.7-1.95V

Symbol

Parameter

LPDDR2 1066

Unit

Min

Max

CCK

Input capacitance :

CK,



CDCK

Input capacitance delta :

CK,



0.2

Input capacitance:

all other input-only pins

CDI

Input capacitance delta:

all other input-only pins

-0.4

0.4

CIO

Input/output capacitance :

DQ, DQS,

, DM

1.25

2.5

CDDQS

Input/output capacitance delta : DQS, 

0.25

CDIO

Input/output capacitance delta : DQ, DM

-0.5

0.5

CZQ

Input/output capacitance : ZQ

2.5

Notes:

1. This parameter applies to die devices only (does not include package capacitance).

2. This parameter is not subject to production testing. It is verified by design and characterization. The capacitance is measured

according to JEP147 (procedure for measuring input capacitance using a vector network analyzer), with VDD1, VDD2, VDDQ

and VSS applied; all other pins are left floating.

3. Absolute value of CCK - .

4. CI applies to , CKE, and CA[9:0].

5. CDI = CI – 0.5 × (CCK + )

6. DM loading matches DQ and DQS.

7. MR3 I/O configuration DS OP[3:0] = 0001B (34.3 ohm typical)

8. Absolute value of CDQS and .

9. CDIO = CIO – 0.5 × (CDQS + ) in byte-lane.

10. Maximum external load capacitance on ZQ pin, including packaging, board, pin, resistor, and other LPDDR2 devices: 5pf.

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