MP7652

7

Rev. 1.00

THEORY OF OPERATION

The MP7652 is a 4-channel multiplying D/A converter that in-

corporates a novel open loop architecture invented by MPS.

The design produces the widest bandwidth, fastest settling time,

most constant group delay, and a very low noise operation

compared to the conventional R-2R based architectures (given

an equal technology platform). This device is particularly useful

in applications where analog multipliers are used to perform the

gain adjustment function for high frequency analog signal condi-

tioning. Analog multipliers produce much higher noise and.

This design allows for digital control of gain with constant and

very low noise for all gain settings.

Linearity Characteristics

Each DAC achieves DNL

 +0.5 LSB (typ), INL  +1 LSB

(typ), and gain error

 +1.5%. Since all 4 channel D/A convert-

ers are fabricated on the same IC, the linearity matching and

gain matching of +0.5% (typ) is achieved.

AC and Low Noise Performance

The novel subranging architecture delivers a 15 MHz (type)

–3 dB bandwidth. A constant group delay of 70 ns (typ) is

achieved to frequencies up to 8 MHz. Analog output settling

settle to 8 bits in less than 110 ns (typ). Note that the AC perfor-

mance specifications also match to between all 4 channels. The

above AC and transient performance is achieved with each

channel consuming only 20 mW (typ) with 10 V p-p supplies.

Serial Port

MP7652 is equipped with a serial data 3-wire standard

µ-proc-

essor logic interface to reduce pin count, package size, and

board wire (space). This interface consists of LD which controls

the transfer of data to the selected DAC channel, SDI (serial

data/address input), CLK (shift register clock) and SDO (serial

data output). When the LD signal is high, CLK signal loads the

digital input bits (SDI) into the 12-bit shift register. The LD signal

going low loads this data into the selected DAC. The LD signal

going low also disables the serial data input (SDI), output (SDO

tri-stated) and the CLK input. This design tremendously re-

duces digital noise, and glitch transients into the DACs due to

free running CLK and SDI. Also, tri-stating the SDO output with

LD signal would allow read back of pre-stored digital data of the

selected package using one SDO wire for all DAC ICs on the

board. When the PRESET signal is low, the output of all DACs

Power Supplies and Voltage Reference DC Voltage

Ranges

8.2 V. Refer to

Table 2. for the relationship equations.

–1.8 = +3.2 V. Refer to

Table 2. for the relationship equations.

I1

Q2

Q1

DAC

+1

Figure 4. Simplified Block Diagram