3.3V Uniform Sector

Dual and Quad Serial Flash

GD25B16C

12

CMP bit

The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4-BP0 bits

to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The

default setting is CMP=0.

HPM bit

The High Performance Flag (HPM) bit indicates the status of High Performance Mode (HPM). When HPM bit sets to 1,

it means the device is in High Performance Mode, when HPM bit sets 0 (default), it means the device is not in High

Performance Mode.

SUS bit

The SUS bit is a read only bit in the status register (S15) that is set to 1 after executing an Erase/Program Suspend

(75H) command. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) command as well as a power-down, power-

up cycle.